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Keywords: IP Design Engineer, Location: San Jose, CA

Page: 1

Sr Principal Design Engineer- Memory IP

. Specific duties include: Be responsible for high-performance memory IP architecture design, owning the IC micro-architecture..., timing budget, power analysis platform development. Proficiency in logic design, simulation, synthesis, STA and testing...

Posted Date: 12 Dec 2025

Principal Design Engineer- Memory IP

. Requires good communication skills in English. Familiar with JEDEC-DDR, and DFI protocols and have memory IP design experience.... Specific responsibilities: Proficiency in logic design and micro-architecture Proficiency in Verilog/SystemVerilog and its...

Posted Date: 12 Dec 2025

ASIC Design Engineer, ML Processor & Digital IP

your career. THE ROLE: As a frontend ASIC Design Engineer, ML Processor & Digital IP you will work on defining... and implementing features in key IPs.. THE PERSON: You have a passion for modern, complex processor architecture, digital design...

Posted Date: 25 Feb 2026

ASIC/SoC Design Engineer, RTL design for SoC IPs

products. As a Senior ASIC Design Engineer, you will own the complete RTL design lifecycle from micro-architecture... specification through production silicon, working on complex IP design. THE PERSON: The ideal candidate is a seasoned ASIC/SOC...

Posted Date: 21 Feb 2026

ASIC/SoC Design Engineer, RTL design for SoC IPs

your career. ASIC DESIGN ENGINEER THE ROLE: Join AMD's Silicon Design team to design and develop cutting-edge IPs... for next-generation embedded products. As a Senior ASIC Design Engineer, you will own the complete RTL design lifecycle from micro...

Posted Date: 08 Feb 2026

IP Design Engineer

your career. THE ROLE: We are looking for a self-motivated senior design engineer to be part of a leading team to drive... timing constraints involving multiple clock domains while working with physical design to harden IP. Help lead and mentor...

Posted Date: 16 Jan 2026

Application Engineer SerDes IP

design IP business. You’ll showcase IP performance through demos at industry events while gaining both technical depth... Cadence IP team develops industry‑leading IP that powers products across markets—from endpoints to the edge to the cloud...

Posted Date: 28 Jan 2026
Salary: $74200 - 137800 per year

IP Verification Engineer DFX

your career. THE ROLE: As an IP verification engineer in the AECG Group, you will help bring to life cutting-edge FPGA, ASICs..., IP design, PD teams, and product engineers to achieve first pass silicon success. THE PERSON: You have a passion...

Posted Date: 05 Mar 2026

IP Verification Engineer PCIe Focus

your career. THE ROLE: As an IP verification engineer in the AECG Group, you will help bring to life cutting-edge FPGA, ASICs..., IP design, PD teams, and product engineers to achieve first pass silicon success. THE PERSON: You have a passion...

Posted Date: 28 Feb 2026

IP Verification Engineer

, IP design, PD teams, and product engineers to achieve first pass silicon success. THE PERSON: You have a passion... for modern, complex IP architectures, digital design, and verification in general. You are a team player who has excellent...

Posted Date: 03 Feb 2026

IP Network Engineer

Are you a skilled Network Engineer with a passion for design? We are partnered with a leading technology solutions... to jointheir dynamic team. As a Senior Network Engineer, you will play a crucial role in maintaining and optimising the network...

Posted Date: 20 Dec 2025

ASIC/RTL Design Engineer - Senior

. Job Title: ASIC/RTL Design Engineer - Senior Work Location: San Jose, CA Duration: 12 Months Work Type: Temporary... portions of the design and implementation of blocks to meet functional, timing, area, and power requirements. Collaborate...

Company: TekWissen
Location: San Jose, CA
Posted Date: 06 Mar 2026

ASIC/RTL Design Engineer - San jose, CA

ASIC/RTL Design Engineer - Senior (US) Location: San Jose, CA 100% onsite (4 days a week in office, Friday optional... RTL block for an SOC. - Must have proven track record of ASIC design on several production tape-outs. - Experience...

Company: Sunrise Systems
Location: San Jose, CA
Posted Date: 05 Mar 2026

FPGA Design Engineer

Position: FPGA Design Engineer Job Description: Location: Mountain View, CA (Remote...) What will you do: Strong expertise on Arteris/ NOC Design Toolset At-least 5+ years of experience in Verilog Design AMBA AXI bus along-with ARM or C...

Location: San Jose, CA
Posted Date: 05 Mar 2026
Salary: $95900 - 203500 per year

FPGA Design Engineer

Position: FPGA Design Engineer Job Description: Location: Mountain View, CA (Remote...) What will you do: Strong expertise on Arteris/ NOC Design Toolset At-least 5+ years of experience in Verilog Design AMBA AXI bus along-with ARM or C...

Location: San Jose, CA
Posted Date: 05 Mar 2026

Principal SoC RTL Design Engineer (remote)

Principal SoC RTL Design Engineer Remote / work from any US location US Citizen or US Permanent Resident Primary..., shell, etc. SoC design flow including chip-level design, block/IP design and behavioral modeling Strong familiarity...

Location: San Jose, CA
Posted Date: 05 Mar 2026

Digital Design Engineer

Edinburgh team is seeking a Principal Digital Design Engineer to grow its talented group located in San Jose, U.S.A. ADI... to enhance both technical expertise and interpersonal skills, whilst collaborating with our design teams worldwide...

Company: Analog Devices
Location: San Jose, CA
Posted Date: 05 Mar 2026

Senior SoC Design Engineer

skilled digital design engineer with deep expertise in modern processor architectures and SoC development. You thrive..., subsystems, and third-party IP into SoC designs. Execute all phases of the SoC design flow, including high-level design...

Posted Date: 04 Mar 2026

Staff Physical Design Engineer

Physical Design Engineer to join our embedded FPGA (eFPGA) IP implementation team. In this role, you will lead the physical..., ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at and on and . Staff Physical Design Engineer...

Company: Analog Devices
Location: San Jose, CA
Posted Date: 04 Mar 2026

Senior Mask Design Engineer

, or thinks? As a Senior Mask Design Engineer in our Research & Development team, you'll have the opportunity to merge creativity... and resolve violations. Participate in layout design of RF circuits (block/IP/chip) floor planning from scratch, performing...

Company: Infineon
Location: San Jose, CA
Posted Date: 04 Mar 2026