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Keywords: IP Verification Engineer, Location: San Jose, CA

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IP Verification Engineer

your career. THE ROLE: As a verification engineer in the AECG Group, you will help bring to life cutting-edge FPGA, ASICs... for modern, complex IP architectures, digital design, and verification in general. You are a team player who has excellent...

Posted Date: 19 Oct 2025

System IP Design Verification Engineer

Job Title: System IP Design Verification Engineer Position Description: Protingent Staffing has an exciting contract... System IP Design Verification Engineer opportunity for our client located in San Jose, CA. Job Description: As a Senior...

Company: Protingent
Location: San Jose, CA
Posted Date: 26 Sep 2025

Design Verification Engineer - External IP

We are seeking a Design Verification Engineer to join our External IP DV team. You will work with vendors, and ensure...Design Verification Team - External IP Team About Etched Etched is building AI chips that are hard-coded...

Company: Etched
Location: San Jose, CA
Posted Date: 13 Sep 2025
Salary: $15000 - 27000 per year

System IP Design Verification Engineer

solutions, Offshore Design Centers (ODCs), and staff augmentation across key areas like RTL Design, UVM Verification, Emulation..., which employs over 32,000 people across 80+ locations globally. We're seeking a Verification Specialist that will be contributing...

Company: Prodapt
Location: San Jose, CA
Posted Date: 24 Sep 2025

System IP Design Verification Engineer

a Verification Specialist that will be contributing directly to validation efforts on advanced system IP such as cache coherency..., UVM Verification, Emulation, FPGA Validation, DFT, RTL-to-GDSII, Physical Design, Mask Layout, and Silicon Bring-up...

Company: Prodapt
Location: San Jose, CA
Posted Date: 23 Sep 2025

Sr. Design Verification Engineer

, Computer Science, or a related field. ✔ 8+ years of SystemVerilog/UVM experience (IP, sub-system, or SoC level verification... solutions, Offshore Design Centers (ODCs), and staff augmentation across key areas like RTL Design, UVM Verification, Emulation...

Company: Prodapt
Location: San Jose, CA
Posted Date: 24 Oct 2025

Sr. Design Verification Engineer

a highly skilled and adaptable engineer to join our dynamic team, focusing on System-on-Chip (SoC) verification. In this role..., UVM Verification, Emulation, FPGA Validation, DFT, RTL-to-GDSII, Physical Design, Mask Layout, and Silicon Bring-up...

Company: Prodapt
Location: San Jose, CA
Posted Date: 23 Oct 2025

Design Verification Engineer

following characteristics and skills What You will Do: As a verification engineer with a knowledge of subsystems and SoCs.... What You Will Bring: Experience in block/IP/sub-system level verification of SoC IPs/ Peripherals; experience in ARM based boot...

Company: Quest Global
Location: San Jose, CA
Posted Date: 18 Oct 2025

Senior ASIC Design Verification Engineer

to talk to you. What you’ll do: As a Senior ASIC Design Verification Engineer, you will be responsible for verifying... and responsibilities include: Lead comprehensive verification planning and execution for fabric-level and full-chip designs, ensuring...

Company: Persimmons
Location: San Jose, CA
Posted Date: 24 Aug 2025

Verification Engineer - New College Grad

Overview: Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional New College Grads... and silicon IP technology shaping the future of data centers and high-performance systems. Rambus offers a flexible work...

Company: Rambus
Location: San Jose, CA
Posted Date: 12 Sep 2025
Salary: $77900 - 144700 per year

Senior Applications Engineer – DDR Design IP

Applications Engineer – DDR Design IP Job Location: San Jose, CA Job Description The Cadence IP team develops industry leading... set the standard on IP products that get integrated in SoCs that power the world’s Data Centers, Automobiles, Cloud...

Posted Date: 11 Oct 2025
Salary: $84000 - 156000 per year

Senior Applications Engineer – DDR Design IP

Applications Engineer – DDR Design IP Job Location: San Jose, CA Job Description The Cadence IP team develops industry leading... set the standard on IP products that get integrated in SoCs that power the world’s Data Centers, Automobiles, Cloud...

Posted Date: 05 Oct 2025
Salary: $84000 - 156000 per year

Lead Applications Engineer – DDR Design IP

Cadence IP team develops industry leading IPs that enable customers in a variety of markets - from the endpoint to the edge... to the cloud. At Cadence we’re helping set the standard on IP products that get integrated in SoCs that power the world...

Posted Date: 05 Oct 2025
Salary: $102900 - 191100 per year

Sr. Silicon Design Engineer

your career. SENIOR SILICON DESIGN ENGINEER THE ROLE: We are looking for an adaptive, self-motivative design verification... engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD...

Posted Date: 24 Oct 2025

Senior Staff Emulation Engineer - ZEBU

are addressed. Familiarity with scripting languages, verification IP protocols are a plus. Should have good analytical, logical... solutions, Offshore Design Centers (ODCs), and staff augmentation across key areas like RTL Design, UVM Verification, Emulation...

Company: Prodapt
Location: San Jose, CA
Posted Date: 24 Oct 2025

Senior Staff Emulation Engineer - ZEBU

-taskers to ensure all aspects of engineering a product are addressed. Familiarity with scripting languages, verification IP..., UVM Verification, Emulation, FPGA Validation, DFT, RTL-to-GDSII, Physical Design, Mask Layout, and Silicon Bring-up...

Company: Prodapt
Location: San Jose, CA
Posted Date: 23 Oct 2025

Senior Network-on-Chip (NoC)/Fabric Engineer

Senior Network-on-Chip (NoC)/Fabric Engineer US Citizen or US Permanent Resident San Jose, California or remote...) across heterogeneous traffic classes. Collaborate with compute, memory, and accelerator IP teams to define interface protocols (AXI...

Location: San Jose, CA
Posted Date: 23 Oct 2025

Senior Power Management Engineer

Senior Power Management Engineer US Citizen or US Permanent Resident San Jose, California or remote... power intent integration, sequencing handshakes, API behavior, and cross domain safety with firmware, verification, RTL...

Location: San Jose, CA
Posted Date: 23 Oct 2025

FPGA Design & Validation Engineer

Engineer to join our cutting-edge engineering team. The ideal candidate will have experience with leading prototyping platforms... such as Veloce, proFPGA CS, HAPS, Protium, proFPGA, and ZeBu. This role requires a proactive engineer with a background in FPGA-based...

Posted Date: 11 Oct 2025

Post-Silicon Validation Engineer

Post-Silicon Validation Engineer About Etched Etched is building AI chips that are hard-coded for individual model... and motivated Post Silicon Validation Engineer to join our dynamic team. The ideal candidate will be responsible for bringing up...

Company: Etched
Location: San Jose, CA
Posted Date: 10 Oct 2025