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Keywords: Lead Applications Engineer – DDR Design IP, Location: San Jose, CA

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Lead Applications Engineer – DDR Design IP

to help us lead the industry with our IP products. At Cadence, we believe in embracing diverse ideas and striving.... As a Lead Technical Presales Engineer, you will use your knowledge of different memory interface standards to architect memory...

Posted Date: 05 Oct 2025
Salary: $102900 - 191100 per year

Senior Applications Engineer – DDR Design IP

Applications EngineerDDR Design IP Job Location: San Jose, CA Job Description The Cadence IP team develops industry leading... and we are looking for smart, energetic, collaborative and creative people to help us lead the industry with our IP products. At Cadence...

Posted Date: 11 Oct 2025
Salary: $84000 - 156000 per year

Sr Principal Product Engineer – Memory IP

. We apply our Intelligent System Design strategy to deliver software, hardware, and IP that turn design concepts into reality. Our customers... Join our growing and dynamic IP team and help lead the proliferation of best-in-class Memory PHY IP products across a wide range...

Posted Date: 23 Nov 2025