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Keywords: Memory Chip Design Engineer, Location: San Jose, CA

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Memory Chip Design Engineer

memory chip designs Capability to develop design layout schedules that meet chip functional requirements and timelines... for the role will include: Developing high density memory chip custom layout Including shared operational circuitry...

Company: Western Digital
Location: San Jose, CA
Posted Date: 04 Feb 2026
Salary: $145800 - 194400 per year

RTL Design Engineer - Intermediate

. Job Title: RTL Design Engineer Intermediate Work Location: San Jose, CA, 95106 Duration: 6+ Months Work Type: Temporary... Network on Chip (NoC), Memory and other subsystems Pre-Si Verification: Perform pre-silicon verification and emulation...

Company: TekWissen
Location: San Jose, CA
Posted Date: 03 Feb 2026

IP Design Engineer

your career. THE ROLE: We are looking for a self-motivated senior design engineer to be part of a leading team to drive..., you will focus on RTL design and validation of high-speed interfaces such as chip-to-chip interconnect, both on system and on package...

Posted Date: 16 Jan 2026

Staff Silicon Design Verification Engineer

your career. THE ROLE: Adaptive and Embedded Computing Group (AECG) seeks a Staff Silicon Design Verification Engineer...: Lead the verification of high-speed Crypto, Network-on-Chip (NoC), cutting-edge DRAM Memory controller (LPDDR6, HBM4...

Posted Date: 15 Jan 2026

Sr. Silicon Design Verification Engineer

your career. THE ROLE: Adaptive and Embedded Computing Group (AECG) seeks a Senior Silicon Design Verification Engineer...: Lead the verification of high-speed Crypto, Network-on-Chip (NoC), cutting-edge DRAM Memory controller (LPDDR6, DDR5...

Posted Date: 08 Jan 2026

R&D ENGINEER IC DESIGN

-chip solutions to market. The group develops ASIC's for L2/L3 switching and routing for various market segments. These.../s to hundreds of Gb/s as well as various line interfaces and protocols. You will be responsible for the micro-architecture, design...

Company: Broadcom
Location: San Jose, CA
Posted Date: 17 Jan 2026
Salary: $120000 - 192000 per year

High-Speed Analog/Mixed-Signal Design Engineer

of next generation IOs, high speed memory (LPDDR5, DDR5, gDDR6, HBM2/HBM3, chip-to-chip,…) and chip-to-chip Gbps proprietary PHY IP... (PCIE, USB, …), parallel high BW memory interface PHY/IOs (DDR4/DDR5, HBM2/HBM3, gDDR5/gDDR6, …) and chip-to-chip links PHY...

Posted Date: 15 Jan 2026

Digital Design Engineer - New College Grad

an exceptional MTS Digitan Design Engineering to join our Memory Interface Chip team in San Jose. In this role, you will be working...Overview: Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire...

Company: Rambus
Location: San Jose, CA
Posted Date: 23 Nov 2025
Salary: $93000 - 172000 per year

Senior Silicon Design Engineer

. Collaborate with processor, interconnect, AI, and memory subsystem architects to ensure cohesive system-level design. Specify... on chip pervasive components, while ensuring seamless integration with processor subsystems, interconnect, AI accelerators...

Posted Date: 08 Nov 2025

Principal Application Engineer

, memory interface chips, DIMM, server and BIOS operation and interaction. The PE System Application Engineer is a Full-Time... design wins. Assist with validation and debug of new memory interface chips for DDR5 servers. Collect and analyze signal...

Company: Rambus
Location: San Jose, CA
Posted Date: 25 Jan 2026

Staff Application Engineer

, memory system design, or related fields (3+ years of focus on DDR5 or similar high-speed memory technologies...Job Description We are seeking an experienced and highly motivated Staff Application Engineer to join our team...

Location: San Jose, CA
Posted Date: 24 Jan 2026
Salary: $145000 - 185000 per year

Senior IC Packaging Engineer

, or memory products. Deep hands-on expertise in Flip-Chip BGA (FCBGA) and System-in-Package (SiP), RDL, silicon interposers... in flip-chip BGA package design and layout. SI/PI expertise preferred, including S-parameter extraction and PDN optimization...

Company: Axiado
Location: San Jose, CA
Posted Date: 18 Jan 2026

Firmware Engineer

Job Requirements POSITION: Firmware Engineer Who We Are: Quest Global delivers world-class end-to-end engineering... by technology and innovation, but also perpetually driven to design, develop, and test as a trusted partner for Fortune 500...

Company: Quest Global
Location: San Jose, CA
Posted Date: 08 Jan 2026
Salary: $100000 - 160000 per year

Principal ASIC Test Development Engineer

ATE-level tests to solve such issues, per strong knowledge of a chip’s design. Responsible for influencing supplier testing...Principal ASIC Test Development Engineer This role has been designed as ‘Hybrid’ with an expectation...

Posted Date: 19 Dec 2025

FPGA HW/SW Codesign Engineer

your career. THE ROLE: Join our team to architect and develop cutting-edge hardware/software co-design solutions for FPGA... AI/ML workloads. You will design high-performance hardware acceleration engines and embedded software that orchestrates them...

Posted Date: 07 Jan 2026

Performance Engineer

Characterize the performance impact of architectural features like specialized datapaths, memory hierarchies, and on-chip...-based models to predict performance under different architectural configurations and design trade-offs Collaborate...

Company: Etched
Location: San Jose, CA
Posted Date: 12 Nov 2025
Salary: $2000 per month

Senior Custom ASIC Engineering Lead

Following skills are nice to have: Exposure to SERDES communications protocols. Logic design, chip architecture...Are you a versatile, senior engineer capable of leading external and internal cross-functional teams in areas...

Company: Broadcom
Location: San Jose, CA
Posted Date: 06 Nov 2025