Job Requirements Lead end-to-end DV activities : Testbench architecture, Test plan, Coding, execution and Sign-off...
Job Requirements Develop and execute Systemverilog/UVM Testbenches for IP Verification Develop Test plan, Implement & run directed, random, and constrained random tests Debug simulation failures and work with RTL team for resolution. ...
Job Requirements Develop and execute Systemverilog/UVM Testbenches for SOC/IP Verification Develop Test plan, Implement & run directed, random, and constrained random tests Write C & SV/UVM based tests Debug simulation failures and wo...
Job Requirements Job Summary: We are looking for a highly skilled and hands on Senior Lead Engineer to lead.... Key Responsibilities: Lead end-to-end DV activities : Testbench architecture, Test plan, Coding, execution and Sign-off...
_ SMTS SILICON DESIGN ENGINEER Drive and lead execution with SOC teams for Design. Drive efficiency on execution of SOC... quality and timely delivery to various teams like DV, DFT, Emulation & PD. Work with the architecture team on high-level arch...
_ Drive and lead execution with SOC teams for Design. Drive efficiency on execution of SOC for integration as well... delivery to various teams like DV, DFT, Emulation & PD. Work with architecture team on high level arch and uArch definition...
difficult DV problems, make room for innovation. You will be working on all aspects of IP/SOC from RTL simulation to post... with ARM/DSP Experience in post silicon/Emulation is big plus. Good communication skills and ability to lead big team...
General Summary: Qualcomm is hiring strong DV engineers to verify high performance and low power CPUs in Bangalore...
Job Requirements Position Overview We are seeking a highly skilled and experienced Design Verification (DV...) Engineer to join our core silicon engineering team. You will be at the forefront of verifying our next-generation, high...
System on Chip (SOC) Digital Design Senior Principal Engineer, who will be responsible for end to end SOC design development... state of the art. About the Role As SOC Design Lead one will be responsible for driving complex SOC project...
_ MTS SILICON DESIGN ENGINEER THE ROLE: The focus of this role in the AECG ASIC organization is to provide hands... features and/or algorithms Lead internal and external teams for RTL design PREFERRED EXPERIENCE: 8+years of experience...
_ MTS SILICON DESIGN ENGINEER THE ROLE: The focus of this role in the AECG ASIC organization is to provide hands... features and/or algorithms Lead internal and external teams for RTL design PREFERRED EXPERIENCE: 8+years of experience...
's in the latest process technology. As a DFT engineer direct responsibilities of the role, but not limited to, working.... Mentor/Siemens Tessent Shell, TestKompress, ATPG coverage debug. Experience in Design Verification (DV) using standard...
_ Silicon Design Verification Engineer (Multiple Levels) The role: An RTL Design Verification Engineer role in our Security... other subsystem applications. The person: A talented hardware/firmware co-design/verification engineer with strong records...
Design Verification Engineer to join the team. #SCHIE Responsibilities: Job responsibilities: The AISiE silicon team... is seeking a qualified and motivated computer or electrical engineer to contribute to the development of high-quality designs...
_ SENIOR SILICON DESIGN ENGINEER THE ROLE (SOC Verification Engineer: GDP DV ): Work on SOC level verification activities... with customer, team members, lead and come up with testplan, code testcases, checkers, UVM agents, scoreboards and assertions...
Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical... sign-off to post silicon bring up. Work closely with RTL, DD, PD, DV and SoC verification teams to integrate the PHY...
, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Marvell is a leading provider..., and the roll of a Principal Engineer in our team is to ensure the overall success of that product. For each individual, the...
team in DCE - CCS - Lead End-to-End SoC DV execution and sign-off - Define and drive improvements in DV processes... Architecture, Chip Lead, Emulation, and Program Management to drive SoC-level DV execution - Partner with Silicon bring-up...
/Career solutions including the CXL product line. What You Can Expect Job Responsibilities: · Lead End-to-End SoC DV..., above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Marvell Data Centre Engineering (DCE...