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Keywords: Design Verification Engineer, Location: Santa Clara, CA

Page: 4

Principal Mixed Signal Design Engineer

electronic design automation (EDA) tools for schematic capture, simulation, layout, and verification, such as Cadence, Synopsys..., or Mentor Graphics. Very good understanding of related areas such as RTL, Firmware, Design Verification, Design for Test...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 06 Dec 2025
Salary: $165630 - 248100 per year

Digital IC Principal Design Engineer

functionality. Collaborate with verification engineer to develop exhaustive test cases to ensure successful design. Work closely... with the design verification and architecture teams to resolve silicon, design, and verification issues. Mentor, guide...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 03 Dec 2025
Salary: $146850 - 220000 per year

Lead Analog SerDes Architect/Design Engineer

from 400G today to 1.6T+ tomorrow. We are seeking a Lead Analog SerDes Architect / Design Engineer to join our team and shape... design flow Experience with full-chip designs, ESDs and verification flows. Preferred Qualifications Familiarity...

Company: Intel
Location: Santa Clara, CA
Posted Date: 03 Dec 2025

FPGA Design Engineer

an experienced FPGA Design Engineer with strong expertise in Xilinx Zynq SoC/MPSoC platforms and practical experience in camera... new chip and advanced display in the world. We design, build and service cutting-edge equipment that helps our customers...

Location: Santa Clara, CA
Posted Date: 28 Nov 2025
Salary: $124000 - 171000 per year

Senior ASIC Design Engineer

We are looking for a Senior ASIC Design Engineer to join our Switch Silicon team. As a Design Engineer at NVIDIA.... Collaborate with architects, verification engineers, formal engineers, physical design engineers, and software engineers...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 20 Nov 2025

Senior Mask Design Engineer - Hardware

, to amplify human creativity and intelligence. Are you a Mask Layout Design Engineer? If yes, We would love to hear... from you! We are looking for a Senior Mask Layout Design Engineer, someone who is excited to join a growing and dynamic group of diverse individuals...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 13 Nov 2025
Salary: $124000 - 195500 per year

Memory PHY RTL Design Engineer

your career. THE ROLE: The Memory PHY team is looking for a passionate and experienced Design Engineer for RTL and Firmware..., complex processor architecture, digital design, and verification in general. You are a team player who has excellent...

Posted Date: 13 Nov 2025

Senior Principal Digital IC Design Engineer

Design Engineer at Marvell, you will be part of the DCE – Connectivity Business Group, contributing to the development...-functional teams and contribute to the continuous improvement of design and verification methodologies. Supervise and mentor...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 12 Nov 2025

RTL Design Engineer - Intermediate

to architecture, design, and documentation for Ips. RTL Development: Design, verify, and validate high-performance logic using System... with the Network on Chip (NoC), Memory and other subsystems. Pre-Si Verification: Perform pre-silicon verification...

Company: Cynet Systems
Location: Santa Clara, CA
Posted Date: 07 Feb 2026
Salary: $53.62 - 58.62 per hour

Analog Design Engineer

-level design, simulation, and verification of analog circuits using Cadence Virtuoso. Design analog building blocks... efficiency. Carry out comprehensive post-layout verification, including Parasitic Extraction (PEX), Design Rule Check (DRC...

Company: OmniVision
Location: Santa Clara, CA
Posted Date: 05 Feb 2026
Salary: $156853 - 160000 per year

IP Logic Design Engineer

through clean design partitioning, clear microarchitectural documentation, reviewing RTL design and verification of features... correct interactions between blocks or Ips Reviews the verification plan and implementation to ensure design features...

Company: Intel
Location: Santa Clara, CA
Posted Date: 04 Feb 2026

ASIC/RTL Design Engineer

in, the design of leading edge SoCs in advanced digital CMOS processes. Our RTL Design Engineers are expected contribute... to all aspects of SoC design including chip definition, architecture development and modeling, development of micro-architectural...

Location: Santa Clara, CA
Posted Date: 23 Jan 2026

Design Engineer - Sensors

devices. Job activities span the ASIC design process from specification definition, high-level design, coding and verification... and route, timing and power use, and verification or similarly for custom circuit design/layout flow. • Utilizes tools...

Company: Qualcomm
Location: Santa Clara, CA
Posted Date: 18 Jan 2026

Senior ASIC RTL Design Engineer

processor architecture, digital design as well as verification/design quality. You are a team player who has excellent... and microarchitecture specification. Should be well versed with RTL design verification, design quality checks, synthesis, timing closure...

Posted Date: 26 Dec 2025

Senior Staff Analog Design Engineer

Work on detailed transistor level design of analog and mixed signal circuits for CMOS image sensors. Oversee the floor... plan and layout to make sure design responded as designed. Perform the whole chip simulation along with the block level...

Company: OmniVision
Location: Santa Clara, CA
Posted Date: 20 Dec 2025

Analog Design Engineer

field with a focus on mixed-signal circuit design. Must have skills in: Digital MOS VLSI circuit design and layout... and active filters. System and transistor-level analysis and design of integrated circuits. Schematic design, simulation...

Company: OmniVision
Location: Santa Clara, CA
Posted Date: 20 Dec 2025
Salary: $156853 - 160000 per year

Principal Interconnect Micro-architect and RTL Design Engineer

and performance/power. In this role the candidate will work with IP and SOC Architecture team, RTL design team, verification team... and design Work closely with Design teams for Area and Floorplan refinement, Verification Test plan reviews, Timing targets...

Posted Date: 17 Dec 2025

Senior Principal Engineer, Physical Design

experience in back-end physical design and verification, including significant leadership roles Proven track record of leading... opportunity to work on both the physical design and methodology for future designs of our next-generation, high-performance...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 13 Dec 2025

Senior ASIC Design Engineer

design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO...NVIDIA is seeking best-in-class ASIC Design Engineers to design and implement the world’s leading SoC's and GPU...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 10 Dec 2025

Analog Design Engineer

and timing analysis, and reliability checks. Interface with cross-functional teams like RTL, Verification and Physical Design... industry. THE PERSON: Ideal candidate would be the one with not only strong circuit design knowledge, but also clear...

Posted Date: 09 Dec 2025