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Keywords: Principal Interconnect Micro-architect and RTL Design Engineer, Location: Santa Clara, CA

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Principal Interconnect Micro-architect and RTL Design Engineer

and performance/power. In this role the candidate will work with IP and SOC Architecture team, RTL design team, verification team..., and physical design team to drive the RTL design and microarchitecture of modular network on chip IPs for AMD Data Center silicon...

Posted Date: 17 Dec 2025