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Keywords: ASIC RTL Design Technical Lead, Location: San Jose, CA

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ASIC RTL Design Technical Lead

RESPONSIBILITIES: As an ASIC Design Engineer, your responsibilities span various aspects of SOC design: Write microarchitecture... your career. THE ROLE: A senior technical contributor that drives end-to-end delivery of SerDes solution directly contributing...

Posted Date: 08 Oct 2025

Senior DFx/RTL Engineer

Silicon One development organization as an ASIC Implementation Technical Lead in San Jose, CA with a primary focus on Design...-for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT...

Company: Cisco Systems
Location: San Jose, CA
Posted Date: 22 Jul 2025

Lead Applications Engineer – DDR Design IP

. As a Lead Technical Presales Engineer, you will use your knowledge of different memory interface standards to architect memory... and synthesis tools · Strong knowledge of ASIC flow, RTL/Verilog · Individual leadership and initiative to manage pre-sales...

Posted Date: 05 Oct 2025
Salary: $102900 - 191100 per year

Senior Applications Engineer – DDR Design IP

Experience on memory subsystem verification and/or performance analysis Strong knowledge of ASIC flow, RTL design in Verilog... Applications Engineer – DDR Design IP Job Location: San Jose, CA Job Description The Cadence IP team develops industry leading...

Posted Date: 05 Oct 2025
Salary: $84000 - 156000 per year

System IP Design Verification Engineer

solutions, Offshore Design Centers (ODCs), and staff augmentation across key areas like RTL Design, UVM Verification, Emulation..., FPGA Validation, DFT, RTL-to-GDSII, Physical Design, Mask Layout, and Silicon Bring-up. Our embedded services include...

Company: Prodapt
Location: San Jose, CA
Posted Date: 24 Sep 2025

System IP Design Verification Engineer

services. We offer turnkey solutions, Offshore Design Centers (ODCs), and staff augmentation across key areas like RTL Design..., UVM Verification, Emulation, FPGA Validation, DFT, RTL-to-GDSII, Physical Design, Mask Layout, and Silicon Bring-up...

Company: Prodapt
Location: San Jose, CA
Posted Date: 23 Sep 2025

FPGA Product Development

understanding of FPGA, IP, or ASIC design and verification processes. Hands-on experience with SystemVerilog, digital design... of product development while aligning technical outcomes with customer needs. KEY RESPONSIBILITIES: Product Inception...

Posted Date: 01 Oct 2025

GPU Project Manager

solutions, Offshore Design Centers (ODCs), and staff augmentation across key areas like RTL Design, UVM Verification, Emulation..., FPGA Validation, DFT, RTL-to-GDSII, Physical Design, Mask Layout, and Silicon Bring-up. Our embedded services include...

Company: Prodapt
Location: San Jose, CA
Posted Date: 24 Sep 2025

GPU Project Manager

services. We offer turnkey solutions, Offshore Design Centers (ODCs), and staff augmentation across key areas like RTL Design..., UVM Verification, Emulation, FPGA Validation, DFT, RTL-to-GDSII, Physical Design, Mask Layout, and Silicon Bring-up...

Company: Prodapt
Location: San Jose, CA
Posted Date: 23 Sep 2025