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Keywords: Timing Signoff Technical Lead, Location: Bangalore, Karnataka

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Timing Signoff Technical Lead

such as Static Timing Analysis, Formal Verification, EM/IR/PDN aspects, Layout Verification, etc. The candidate..., size/complexity of products and the size of the team. The ideal candidate will have the skills and experience to lead SoC...

Company: Intel
Posted Date: 21 Dec 2025

STA/Timing Methodology Engineer(Senior/Lead)

, convergence, reviews and signoff for multi-mode, multi-voltage domain designs. Timing analysis, validation and debug...+ years of Hardware Engineering or related work experience. Overview: Experienced STA/Timing Engineer with 8-12 Years...

Company: Qualcomm
Posted Date: 19 Dec 2025

Technical Lead I - VLSI

– 2 3. Designation/ band – Technical Lead I – VLSI – B1 4. Mandatory Skill – RTL Design Lead 5. Location – Bangalore JD.../Design Checks/Signoff etc. Anticipate diagnose and resolve problems; coordinating as necessary with cross-functional teams...

Company: UST
Posted Date: 03 Dec 2025

Technical Lead I - VLSI PD CAD

floorplanning, placement, clock tree synthesis (CTS), and routing.  Familiarity with timing closure and DRC/LVS signoff.../Design Checks/Signoff etc. Anticipate diagnose and resolve problems; coordinating as necessary with cross-functional teams...

Company: UST
Posted Date: 17 Dec 2025

Lead Logic Design Engineer Core Microarchitect

with other Core units, Verification, DFT, Physical design, Timing, FW, SW teams to develop the feature - Signoff the Pre-silicon..., DFT, Physical design, Timing, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the...

Company: IBM
Posted Date: 12 Dec 2025

Soc Physical design Tile Lead

or Hierarchical top level for at least few tape outs. Must have led physical design team/s in the capacity of technical lead... for Timing, Calibre for DRC/LVS, Ansys Redhawk on EMIR, PT-PX for Power signoff Should have worked as a go to person...

Posted Date: 11 Dec 2025

Display Synthesis Sr/Lead/Staff

strong leader with an eye for quality to lead a high performing and talented team of engineers in the implementation domain... and performance. Able to grow the team in terms of technical depth and size as we do more and more projects Able to innovate...

Company: Qualcomm
Posted Date: 20 Nov 2025

Power Convergence Lead Physical Design

for Timing, Ansys Redhawk on EMIR, PT-PX for Power signoff Should have worked as a go-to person or technical lead... Design, Timing Analysis, Synthesis, Logical equivalence, Physical Verification, Power design/implementation/signoff...

Posted Date: 17 Nov 2025

Lead MTS Physical Design

an exceptional Lead Static Timing Analysis Engineer to join our STA team in Bangalore. In this role, you will be working...: * Complete ownership of Static timing analysis at full chip level for high speed mixed signal design Experience doing multi-mode...

Company: Rambus
Posted Date: 31 Oct 2025

STA Synthesis Sr Engineer/Lead/Staff

strong leader with an eye for quality to lead a high performing and talented team of engineers in the implementation domain... and performance. Able to grow the team in terms of technical depth and size as we do more and more projects Able to innovate...

Company: Qualcomm
Posted Date: 12 Oct 2025

Lead Physical design, Physical Implementation, STA

, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis... analytical and problem-solving skills. You have excellent communication and presentation skills, demonstrated through technical...

Posted Date: 08 Nov 2025

Staff Engineer Digital Design Engineer

-Electronics Location : Bangalore, India Job Grade : P4 Rssponsibilities: Lead and develop timing methodologies, establish... technical guidance to elevate team proficiency and performance. Desired Skills: Proven ability in timing analysis...

Posted Date: 18 Dec 2025

Staff Engineer Digital Design Engineer

-Electronics Location : Bangalore, India Job Grade : P4 Rssponsibilities: Lead and develop timing methodologies, establish... technical guidance to elevate team proficiency and performance. Desired Skills: Proven ability in timing analysis...

Posted Date: 17 Dec 2025

Associate III - VLSI STA

/Synthesis/Design Checks/Signoff etc. Independently analyze and complete the assigned task in the defined domain(s) successfully... and on-time On time quality delivery approved by the project lead/manager Measures of Outcomes: * Quality –verified using...

Company: UST
Posted Date: 17 Dec 2025

Associate III - VLSI DFT_N

/Synthesis/Design Checks/Signoff etc. Independently analyze and complete the assigned task in the defined domain(s) successfully... and on-time On time quality delivery approved by the project lead/manager Measures of Outcomes: * Quality –verified using...

Company: UST
Posted Date: 17 Dec 2025

Senior Principal Engineer, Physical Design

closure, power/signal integrity signoff, and physical verification (DRC/LVS). Provide strategic leadership and technical..., above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Built on decades of expertise...

Company: Marvell
Posted Date: 13 Dec 2025

IBM SENIOR LOGIC DESIGN ENGINEER - Memory Management Unit

that meets all the functional, area and timing goals - Participate in silicon bring-up and validation of the hardware - Lead.... - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in silicon bring-up...

Company: IBM
Posted Date: 12 Dec 2025

Staff Synthesis & STA Engineer

About the Role As a Staff Synthesis & STA Engineer, you will own lead & own Synthesis & STA for complex high performance ICs... with large digital & analog interfaces. You'll influence implementation, guide methodology improvements, and lead small...

Posted Date: 12 Dec 2025

SOC Physicla design Floorplan Architect

, PT-PX for Power signoff Should have worked as a go to person or technical lead for at least few full chip projects... or Hierarchical top level for at least few tape outs. Must have led physical design team/s in the capacity of technical lead...

Posted Date: 11 Dec 2025

Principal Engineer - SOC Clocking

Job Details: Job Description: Key Responsibilities: Lead the architecture, design, and integration of SoC-wide... with RTL, physical design, verification, and DFT teams to deliver end-to-end SoC clocking and custom IP. Own the technical...

Company: Intel
Posted Date: 10 Dec 2025