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Keywords: Testbench/Verification Engineer, Location: Santa Clara, CA

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Testbench/Verification Engineer

The Role: Testbench/Verification Engineer for the Infinity Fabric team. The Fabric IP is a flexible and scalable high... and verification engineer with exceptional programming skills, System Verilog and UVM experience, proven experience with working...

Company: Managed Staffing
Location: Santa Clara, CA
Posted Date: 07 Nov 2025

Testbench/Verification Engineer

The Role: Testbench/Verification Engineer for the Infinity Fabric team. The Fabric IP is a flexible and scalable high... and verification engineer with exceptional programming skills, System Verilog and UVM experience, proven experience with working...

Company: Managed Staffing
Location: Santa Clara, CA
Posted Date: 06 Nov 2025

Testbench/Verification Engineer

Job Description: Pay Range: $70hr - $86hr The Verification Engineer will be responsible for developing, enhancing... in verification and testbench flows, with strong hands-on experience in SystemVerilog and UVM frameworks. Skilled in debugging...

Company: Cynet Systems
Location: Santa Clara, CA
Posted Date: 04 Nov 2025

ASIC Design Verification Engineer (Santa Clara, CA)

and products. This is the Invention Age - and this is where you come in as an ASIC Design Verification Engineer The team... is responsible for the complete verification lifecycle, from system-level concept to tape out and post-silicon support. The...

Company: Qualcomm
Location: Santa Clara, CA
Posted Date: 23 Oct 2025

Custom SOC IP Verification Engineer

NVIDIA is seeking a Senior Custom SOC/IP Verification Engineer to verify the next generation SoC and IP solutions... a skilled ASIC Verification Engineer with expertise in cache coherency protocols and AMBA-based interconnects (AXI, ACE, CHI...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 21 Sep 2025

CPU Top-Level Design Verification Engineer

Top-Level Design Verification Engineer owning the verification methodology, tools, and flow of a high performance lower... verification methodology • Developing, verifying, and maintaining efficient testbench environments • Develop coverage monitors...

Company: Apple
Location: Santa Clara, CA
Posted Date: 18 Sep 2025
Salary: $126800 - 190900 per year

CPU Top-Level Design Verification Engineer

Top-Level Design Verification Engineer owning the verification methodology, tools, and flow of a high performance lower... verification methodology • Developing, verifying, and maintaining efficient testbench environments • Develop coverage monitors...

Company: Apple
Location: Santa Clara, CA
Posted Date: 18 Sep 2025

Senior Verification Engineer - CPU

We are now looking for a Senior Verification Engineer! As a member of our CPU Verification Team..., you will be responsible for a portion of the Design Verification, focusing on tasks such as testbench/scoreboard/stimulus development...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 21 Aug 2025

Functional Verification Senior Staff Engineer

_ THE ROLE: We are looking for an adaptive, self-motivative design verification engineer to join our growing team.... Develop tools, infrastructure, processes and flows to enable functional verification Document testplans and testbench...

Posted Date: 21 Aug 2025

Staff Verification Engineer

-power techniques. What You Can Expect In this role, you will architect and develop a functional verification environment.... Activities may include: - Writing a verification test plan that employs random techniques, directed testing, and coverage...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 25 Oct 2025
Salary: $105470 - 158000 per year

Senior ASIC Verification Engineer - GPU

NVIDIA is seeking best-in-class ASIC Verification Engineers to verify the world’s leading GPUs. In this role..., you will be doing unit level verification of the process scheduling and system interface hardware of the GPU. This position...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 11 Oct 2025

Principal Engineer, Design Verification

-power techniques. What You Can Expect In this role, you will architect and develop a functional verification environment.... Activities may include: - Writing a verification test plan that employs random techniques, directed testing and coverage...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 30 Sep 2025
Salary: $146850 - 220000 per year

Design Verification Intern - Bachelor's Degree

company, etc. What You Can Expect In this in-office role in Santa Clara, CA, you’ll work day-to-day with an RTL engineer... and you can write and debug a testbench. - Be comfortable working in a Linux environment and doing scripting with Python...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 19 Oct 2025
Salary: $27 - 53 per hour

Interconnect RTL Design Engineer

has its own custom-designed Infinity Data Fabric, so this role gives an engineer the opportunity to work on a broad array... PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general...

Posted Date: 24 Aug 2025