Keywords: Staff Engineer, VLSI Design Engineering (SOC, Verification, UVM), Location: Bangalore, Karnataka

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Staff Engineer, VLSI Design Engineering (SOC, Verification, UVM)

for SoC Create verification environment using UVM methodology Hands on in end to end Logic Verification Process including..., porting and maintaining System Verilog Assertions including Formal Verification Development of tools for Design...

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Company: SanDisk

Location: Bangalore, Karnataka

Posted Date: 30 Dec 2025

Staff Engineer, VLSI Design Engineering (SOC Verification, System Verilog, UVM)

. Job Description We are looking for a highly motivated engineer to develop synthesizable RTL models, validate them using UVM testbenches, and deliver optimized... integration issues. Qualifications Qualifications: 4 to 7 years of experience in RTL design, UVM validation, and emulation...