BE/ME in ECE, Electronics, or a related engineering discipline. 5–7 years of hands-on experience in RTL verification... at Block/IP/Sub-system/SoC levels. Proficient in SystemVerilog for verification; advanced experience with SVA and UVM...
knowledge of ASIC design and development, including digital design, verification methodologies, and proficiency in hardware... in IP / blocks / subsystem complex design in verilog / system verilog Strong digital design development and execution...
. Job Description Position Overview: We are seeking a highly skilled and experienced Staff Engineer for our Static Timing Analysis (STA... level STA , providing direction and guidance to PnR team for Timing closure & Synthesis report analysis. - Work with IP...
Design and develop RTL in Central Engineering team for products which includes blocks such as wakeup sequencing..., calibration logic, I3C/I2C protocol, interrupt controller, EEPROM, MCU integration etc. Work with Pre/Post-silicon verification...
Job Category: Engineering Degree Level: Masters Job Description: We are seeking an experienced ASIC Verification... within a diverse team environment. #LI-RG1 Responsibilities: We are seeking an experienced ASIC Verification Engineer...
field. Required Skills & Experience 5+ years of experience in IP verification for ASIC designs. Strong expertise... for optimization of designs. The Sr. Engineer will interface with internal staff and outside partners in the fast-paced execution...