with TSMC 3/4/5nm technology. Experience with layout of analog blocks ADC / DAC / PLLs. Experience with 112G SerDes layout... and Layout Designers on chip layout and custom analog and RFIC IP blocks in technologies down to 3 nm. Location: 100% on-site...
with TSMC 3/4/5nm technology. Experience with layout of analog blocks ADC / DAC / PLLs. Experience with 112G SerDes layout... and Layout Designers on chip layout and custom analog and RFIC IP blocks in technologies down to 3 nm. Location: 100% on-site...