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Keywords: SoC RTL Design Engineer, Location: Austin, TX

Page: 3

Data Cache & Coherent Interconnect Architect/Engineer (Multiple Levels)

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group DSP Architecture and Design..., you will be responsible for architecture definition, performance modeling, analysis, and RTL implementation of cache and interconnect...

Company: Qualcomm
Location: Austin, TX
Posted Date: 24 Jul 2025

Power and Performance Attainment and Feature Enablement Lead

and architecture at micro-architecture, L2/L3 cache design hierarchy, and core complex CCX-level. Understands physical design and RTL... environment. Experience in SoC design, validation, or power optimization, with a focus on pre- and post-silicon power management...

Location: Austin, TX
Posted Date: 29 Aug 2025