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Keywords: SoC Design Verification Engineer, Location: Santa Clara, CA

Page: 2

ASIC Clocks Design Engineer - New College Grad 2025

, we deliver clock RTL information to GPU, CPU and SOC verification team, timing and DFT teams. Get involved in end-to-end cycle.... Experience in RTL design (Verilog), verification and logic synthesis. Strong coding skills in python or other industry-standard...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 27 Sep 2025
Salary: $108000 - 184000 per year

ASIC/RTL Design Engineer - Senior (San Jose, Ca) - AMDJP00004484

Position Title: ASIC/RTL Design Engineer Location: Santa Clara, CA Position Status: Contract Pay Rate: 75/hr... of leading edge SoCs in advanced digital CMOS processes. Our RTL Design Engineers are expected contribute in all aspects of SoC...

Company: Seneca Resources
Location: Santa Clara, CA
Posted Date: 25 Sep 2025
Salary: $75 per hour

Sr. Silicon Design Engineer

_ Job Role and Responsibility: AMD, Inc., is hiring Sr. Silicon Design Engineer to Research, design, develop, and/or test.... Oversee definition, design, verification, and/or documentation for ASIC development. Determine architecture design, logic...

Posted Date: 21 Sep 2025

Sr. Silicon Design Engineer

_ Job Role and Responsibility: AMD, Inc., is hiring Sr. Silicon Design Engineer to Research, design, develop, and/or test.... Oversee definition, design, verification, and/or documentation for ASIC development. Determine architecture design, logic...

Posted Date: 21 Sep 2025

Digital Design Engineer, Principal

to design, validate, and optimize sophisticated, timing-critical systems—mastering every stage of the SoC front-end design flow.... We develop the architecture, collaborate on IP development, create the physical design, and work with the world’s leading AI data...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 19 Sep 2025
Salary: $146850 - 220000 per year

GPU Design Engineer - Memory Hierarchy

help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You'll...! Description As a GPU Design Engineer, you will participate in micro-architecture specification and RTL coding. Explore architecture trade...

Company: Apple
Location: Santa Clara, CA
Posted Date: 14 Sep 2025
Salary: $126800 - 190900 per year

IC Package Design Engineer

. Description - Implement the physical design of packages and modules for SoC, Memory, RF, and cellular chips. - Interface and coordinate.... - Define and develop design verification and automation strategy to strengthen and streamline package design as well as release...

Company: Apple
Location: Santa Clara, CA
Posted Date: 04 Sep 2025

ASIC Design Engineer

NVIDIA is looking for an ASIC Design Engineer to join our Memory Subsystem Team! As an ASIC Design engineer at NVIDIA... RTL design, synthesis, functional verification and timing analysis using innovative CAD tools and using the latest process...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 29 Aug 2025
Salary: $108000 - 184000 per year

Design-for-Test (DFT) Engineer

, secure, and performance-optimized compute. As a Design-for-Test Engineer, you’ll help ensure silicon reliability and debug... across the chip lifecycle. You'll collaborate cross-functionally with design, verification, and physical design teams...

Company: Initio Capital
Location: Santa Clara, CA
Posted Date: 04 Aug 2025

Senior ASIC Design Engineer

NVIDIA is seeking an outstanding Senior ASIC Design Engineer to design and implement the world’s leading SoC's and GPU... with verification engineers. Deliver a synthesis/timing clean design while working with the physical design team to ensure a routable...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 31 Jul 2025

Senior ASIC Design Engineer – Clocks IP

, we deliver clock RTL information to GPU, CPU and SOC verification team, timing and DFT teams. Get involved in end-to-end cycle... and ability to collaborate with multiple teams. Experience in RTL design (Verilog), verification and logic synthesis...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 31 Jul 2025

SRAM Circuit Design Engineer

team to create optimal GDS. - Verify extracted GDS meets design specifications. - Backend verification, IR/EM - Write RTL... We are looking for applicants with interest in the SoC design cycle, developing circuits and SRAM/Register File for low power, low voltage and high...

Company: Apple
Location: Santa Clara, CA
Posted Date: 27 Sep 2025
Salary: $121300 - 183200 per year

MTS Silicon Design Engineer

. Oversee definition, design, verification, and/or documentation for ASIC development. Determine architecture design, logic... in the following: 1.SOC or system architecture; 2.Verilog, SystemVerilog, VHDL, or UVM; 3.Functional verification...

Posted Date: 21 Sep 2025

MTS Silicon Design Engineer

verification, design flows and methodologies used for chip verification, graphics IP architecture verification, or functional... verification of microprocessors; and RTL design/coding, logic and circuit design, memory system design, or ASIC design. #LI-DP1...

Posted Date: 20 Sep 2025

Principal Silicon Design Engineer

experience in reusable verification methodology such as UVM Have hands-on experience in SOC Design/Integration activities... and IP level design, SOC architecture and implementation strategies. THE PERSON: Excellent communication and presentation...

Posted Date: 20 Sep 2025

SRAM Circuit Design Engineer

team to create optimal GDS. - Verify extracted GDS meets design specifications. - Backend verification, IR/EM - Write RTL... We are looking for applicants with work experience within a SoC design cycle, developing circuits and SRAM/Register File for low power, low voltage...

Company: Apple
Location: Santa Clara, CA
Posted Date: 17 Aug 2025

Senior Principal Analog Mixed-Signal IC Design Engineer

and performing design verification using industry standard tools such as SPICE, Spectre, MATLAB etc. Should be comfortable carrying... with digital and SOC teams to facilitate design integration and cross-functional verifications. What We're...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 16 Aug 2025

Senior Principal Digital IC Design Engineer

microprocessors. RTL design experience, synthesis, static-timing closure, formal verification, gate-level simulations, and block...-level functional verification. Experience in implementation/timing closure for high speed design. Hands-on experience...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 14 Aug 2025

Senior Physical Design Engineer

looking for Physical design Engineers with RTL2GDS experience to implement complex high performance and low power SOC’s. What you'll... timing constraints. Debugging timing violations and rolling in functional, Timing ECO’s and netlist formal verification...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 25 Jul 2025

Digital Layout Design Engineer

. Description Imagine yourself at the center of our SOC design effort, collaborating with all fields, playing a strategic role of getting... a complete set of layout design verification tools available on megacells completed. - Working with the circuit design team...

Company: Apple
Location: Santa Clara, CA
Posted Date: 10 Jul 2025