Find your dream job now!

Click on Location links to filter by Job Title & Location.
Click on Company links to filter by Company & Location.
For exact match, enclose search terms in "double quotes".

Keywords: Signoff Static Timing Analysis CAD Engineer, Location: San Diego, CA

Page: 1

Signoff Static Timing Analysis CAD Engineer

powering billions of mobile devices. The position requires Signoff Static Timing Analysis (STA) knowledge, with CAD development... Summary: Join QCOM Technologies Inc vibrant Global CAD team pushing the limits of Signoff solutions for the Snapdragon chips...

Company: Qualcomm
Location: San Diego, CA
Posted Date: 19 Oct 2025
Salary: $98500 - 147700 per year

Signoff Static Timing Analysis and Spice CAD Engineer

powering billions of mobile devices. The position requires Signoff Timing and spice simulation experience, with CAD development... Summary: Join QCOM Technologies Inc vibrant Global CAD team pushing the limits of Signoff solutions for the Snapdragon chips...

Company: Qualcomm
Location: San Diego, CA
Posted Date: 19 Sep 2025
Salary: $98500 - 147700 per year

HW SOC/ASIC Physical Design Engineer, Principal

and modes using static timing analysis (STA) tools (e.g., PrimeTime). Collaborate with RTL designers to resolve timing...-level static timing analysis (STA) using industry-standard tools (e.g., Synopsys PrimeTime, Cadence Tempus). Develop...

Company: Qualcomm
Location: San Diego, CA
Posted Date: 19 Oct 2025

HW SOC/ASIC Physical Design Engineer, Staff/Sr Staff

and modes using static timing analysis (STA) tools (e.g., PrimeTime). Collaborate with RTL designers to resolve timing...-level static timing analysis (STA) using industry-standard tools (e.g., Synopsys PrimeTime, Cadence Tempus). Develop...

Company: Qualcomm
Location: San Diego, CA
Posted Date: 19 Oct 2025

HW SOC/ASIC Physical Design Engineer, Senior

across multiple corners and modes using static timing analysis (STA) tools (e.g., PrimeTime). Collaborate with RTL designers...-level static timing analysis (STA) using industry-standard tools (e.g., Synopsys PrimeTime, Cadence Tempus). Develop...

Company: Qualcomm
Location: San Diego, CA
Posted Date: 19 Oct 2025
Salary: $115600 - 173400 per year

Design Methodology Engineer

in die-level IR drop, STA, and power. The engineer should be proficient in static timing analysis using the Synopsys Primetime... ⦁ Develop strategies for 3DIC PDN analysis and signoff Required Skills and Experience : ⦁ Expertise in static timing...

Company: Qualcomm
Location: San Diego, CA
Posted Date: 20 Sep 2025