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Keywords: Senior System Level Test Engineer, Location: Santa Clara, CA

Page: 6

Design Verification Engineer

on system-level memory architecture, identify potential integration issues, and define validation requirements early in the... Modules). The ideal candidate will possess expert-level knowledge of SystemVerilog, UVM, C/C++, and scripting languages...

Posted Date: 28 Jan 2026

Principal Interconnect Micro-architect and RTL Design Engineer

, Virtualization and Security Experience analyzing CPU, GPU or System-level Micro-Architectural features to identify performance... and design Work closely with Design teams for Area and Floorplan refinement, Verification Test plan reviews, Timing targets...

Posted Date: 16 Dec 2025