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Keywords: Senior Physical Design Methodology Engineer, PPA Fusion Compiler, Location: Santa Clara, CA

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Senior Physical Design Methodology Engineer, PPA Fusion Compiler

Senior Physical Design Methodology Engineer, PPA Fusion Compiler to join our outstanding Networking Silicon engineering team... unique and creative solutions to the state-of-the-art physical design problems to improve PPA Knowledge and experience...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 21 Jan 2026

Physical Design Methodology Engineer

RESPONSIBLITIES: Physical design and signoff methodology development for advanced nodes and High performance Automation to improve... and Route, Timing Analysis, and Physical Verification tools from Synopsys, Cadence, like ICC2, Fusion Compiler, DSO.AI, Innovus...

Posted Date: 09 Nov 2025

SOC IP Methodology Engineer - Custom SOC

Nvidia is hiring a Senior SOC/IP Methodology Engineer to help design and architect next generation custom SoC/IP.... Extensive leadership experience as Methodology and Technical expert in physical design working with internal and external...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 22 Jan 2026