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Keywords: SOC Design Verification Engineer, Location: Santa Clara, CA

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Senior Principal Digital IC Design Engineer

Design Engineer at Marvell, you will be part of the DCE – Connectivity Business Group, contributing to the development...-functional teams and contribute to the continuous improvement of design and verification methodologies. Supervise and mentor...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 11 Nov 2025

Digital IC design Engineer

Engineer with Marvell, you’ll be a member of the Custom compute and solutions group. Our design team works on state-of-the-art... verification. Experience in implementation/timing closure for high-speed design. Hands-on experience for all aspects of the...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 08 Nov 2025
Salary: $121400 - 181800 per year

Digital, Mixed Signal IC Design Engineer, Principal

other chip companies and big tech companies, familiar names to all candidates. What You Can Expect ASIC design engineer... responsible for the design, verification and evaluation of digital circuits in high-speed data communication ICs. The candidate...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 07 Nov 2025
Salary: $146850 - 220000 per year

GPU Design Engineer - Memory Hierarchy

help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You'll...! Description As a GPU Design Engineer, you will participate in micro-architecture specification and RTL coding. Explore architecture trade...

Company: Apple
Location: Santa Clara, CA
Posted Date: 06 Nov 2025

GPU Design Engineer - Memory Hierarchy

help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You'll...! Description As a GPU Design Engineer, you will participate in micro-architecture specification and RTL coding. Explore architecture trade...

Company: Apple
Location: Santa Clara, CA
Posted Date: 05 Nov 2025
Salary: $126800 - 190900 per year

ASIC Design Engineer - New College Grad 2025

NVIDIA is looking for an ASIC Design Engineer to join our Memory Subsystem Team! As an ASIC Design engineer at NVIDIA...-architecture and design including RTL design, synthesis, functional verification and timing analysis using innovative CAD tools...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 30 Oct 2025
Salary: $108000 - 184000 per year

Senior ASIC Design Engineer – Clocks IP

, we deliver clock RTL information to GPU, CPU and SOC verification team, timing and DFT teams. Get involved in end-to-end cycle... and ability to collaborate with multiple teams. Experience in RTL design (Verilog), verification and logic synthesis...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 29 Oct 2025

Senior ASIC Design Engineer - DFX

architecture, design, and verification of DFT IPs for cutting-edge SoC designs. Develop, deploy, and enhance DFT methodologies... Engineering or related field. 5+ years of hands-on experience in SoC architecture, RTL design, and verification...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 25 Oct 2025

Digital IC Design Staff Engineer

and integrate IPs for System-on-Chip SoC solutions using state-of-art IC design methodologies, clock domain crossing (CDC)-based... design and application-specific integrated circuit (ASIC) design flows. Perform RTL coding and functional verification...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 07 Oct 2025
Salary: $105470 - 158000 per year

Principal Physical Design Engineer

's Central Physical Design team, you’ll provide backend design services to Marvell's SoC groups, working across a variety... and targeted at the forefront of data infrastructure. What You Can Expect As a Principal Physical Design Engineer specializing...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 05 Oct 2025
Salary: $146850 - 220000 per year

Principal Interconnect Micro-architect and RTL Design Engineer

and performance/power. In this role the candidate will work with IP and SOC Architecture team, RTL design team, verification team... and design Work closely with Design teams for Area and Floorplan refinement, Verification Test plan reviews, Timing targets...

Posted Date: 17 Dec 2025

Senior Principal Engineer, Physical Design

SoC programs, overseeing synthesis, floorplanning, power grid design, place and route, clock tree synthesis, timing... experience in back-end physical design and verification, including significant leadership roles Proven track record of leading...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 13 Dec 2025

Senior ASIC Design Engineer

NVIDIA is seeking best-in-class ASIC Design Engineers to design and implement the world’s leading SoC's and GPU... design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 10 Dec 2025

DFT Design Engineer

for physical implementation. Reviews the verification plan and drives verification of the DFT design to achieve desired... to: Develops the logic design, register transfer level (RTL) coding, simulation, and provides DFT timing closure support as well...

Company: Intel
Location: Santa Clara, CA
Posted Date: 10 Dec 2025

DFT Design Engineer

for physical implementation. Reviews the verification plan and drives verification of the DFT design to achieve desired... to: Develops the logic design, register transfer level (RTL) coding, simulation, and provides DFT timing closure support as well...

Company: Intel
Location: Santa Clara, CA
Posted Date: 10 Dec 2025

ASIC Design Engineer - New College Grad 2026

NVIDIA is seeking ASIC Design Engineers to implement the world’s leading SoC's and GPU's. This position offers the... development (Verilog). Good understanding of ASIC design flow including RTL design, verification, logic synthesis and timing...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 19 Nov 2025
Salary: $96000 - 161000 per year

Physical Design Methodology Engineer

related to Artificial Intelligent/ High Performance Computing SOCs . As a member of the Physical design and SOC teams... design PPA (Power, Performance, Area) and ensure a high-quality design environment for an SOC Full chip / sub-system/ Tile...

Posted Date: 09 Nov 2025

Physical Design Engineer Intern - Bachelor's Degree

, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Marvell CCDS (Central CAD and Design... Services) PD engineers are working on cutting edge SoC (System on a Chip), ASIC, High Performance Processor, Digital/Analog...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 30 Oct 2025
Salary: $27 - 55 per hour

Senior Principal Digital IC Design Engineer

, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Our design team works on state...-of-the-art datacenter and AI SOCs. As a member of the R&D team, you will design world-class hardware for the industry...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 30 Oct 2025

SRAM Circuit Design Engineer

team to create optimal GDS. - Verify extracted GDS meets design specifications. - Backend verification, IR/EM - Write RTL... We are looking for applicants with work experience within a SoC design cycle, developing circuits and SRAM/Register File for low power, low voltage...

Company: Apple
Location: Santa Clara, CA
Posted Date: 16 Oct 2025