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Keywords: RTL Engineer, Location: Santa Clara, CA

Page: 2

Product Engineer - Tessent DFT

as Product Engineer, specializing in design-for-test (DFT). Tessent is the market and technology leader of automated tools... a plus: RTL coding and verification using Verilog/SystemVerilog/VHDL Synthesis and timing analysis Place and route Advanced IC...

Company: Siemens
Location: Santa Clara, CA
Posted Date: 12 Dec 2025
Salary: $129600 - 233300 per year

ASIC Clocks Design Engineer - New College Grad 2025

ASIC engineer to join the team. The Team is responsible for crafting all aspects of GPU and CPU clocking. The team... of timing closure to innovate and implement new Clocking topologies in RTL. Collaborate with Physical design and timing team...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 11 Dec 2025
Salary: $108000 - 184000 per year

Senior SOC Design Engineer

NVIDIA is looking for a Senior SOC Design Engineer to join our SOC Design team! At NVIDIA, you'll collaborate... with brilliant minds to build cutting-edge GPUs and SOCs that power everything from AI to gaming! As a Senior SOC Design Engineer...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 10 Dec 2025

Senior C++ Software Engineer - Chip Design Tools

and support of infrastructure tools used by design engineers for build and verification of architectural, rtl, and gate level... designs. As a software engineer, you will craft highly efficient software to automate and facilitate chip design...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 10 Dec 2025

Principal Mixed Signal Design Engineer

Engineer with Marvell, you’ll be a member of the Central Engineering business group. If you picture Marvell as a wheel, Marvell..., or Mentor Graphics. Very good understanding of related areas such as RTL, Firmware, Design Verification, Design for Test...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 06 Dec 2025
Salary: $165630 - 248100 per year

GPU Prototype and Validation Engineer, Staff

experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm GPU Engineer... methodology to improve the area/performance of the synthesized FPGA RTL. System level RTL simulation & design verification...

Company: Qualcomm
Location: Santa Clara, CA
Posted Date: 05 Dec 2025

Senior Staff Physical Verification CAD engineer - EDA Tools

and experienced Senior Staff Level Physical Verification CAD Engineer to join our dynamic team. The ideal candidate will have a deep... of the complete IC design flow, from front-end design (RTL, synthesis, simulation) to back-end physical implementation (place...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 04 Dec 2025
Salary: $124420 - 186400 per year

Digital IC Principal Design Engineer

Engineer at Marvell, you will be a member of the Custom Compute Solution IP development team. This team develops uniquely high.... What You Can Expect Oversee a team of engineers to develop and verify RTL design for CPU subsystems, co-processor/accelerator...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 03 Dec 2025
Salary: $146850 - 220000 per year

FPGA Design Engineer

an experienced FPGA Design Engineer with strong expertise in Xilinx Zynq SoC/MPSoC platforms and practical experience in camera... using Vivado, IP Integrator, and Vitis. Develop RTL modules in VHDL/Verilog for Zynq PL or Xilinx FPGA. Build...

Location: Santa Clara, CA
Posted Date: 28 Nov 2025
Salary: $124000 - 171000 per year

Senior Formal Verification Engineer

to do their best work. Come join the team and see how you can make a lasting impact on the world. As a Formal Verification Engineer..., or bounded proofs with sufficient coverage. Drive formal tools to realize their best performance. Debug RTL to identify...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 27 Nov 2025

ASIC Design Engineer - New College Grad 2025

We are now looking for an ASIC Design Engineer! NVIDIA has been transforming computer graphics, PC gaming... and see how you can make a lasting impact on the world. Join NVIDIA as an ASIC Design Engineer, influencing product lines spanning...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 26 Nov 2025
Salary: $96000 - 161000 per year

Senior ASIC Design Engineer

We are looking for a Senior ASIC Design Engineer to join our Switch Silicon team. As a Design Engineer at NVIDIA... design team, you will implement, document and deliver high performance, area and power efficient RTL to achieve design...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 20 Nov 2025

Senior Circuit Design Engineer - Power Modeling and Simulation

as a leader in this next wave of computing. We are now looking for a motivated Senior Circuit Design Engineer in Power Modeling..., verilogAMS, mixed-signal RTL+spice, s-parameters, etc. Familiarity/experience with industry-standard design and EDA tools...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 19 Nov 2025

Senior Principal Digital IC Design Engineer

Design Engineer at Marvell, you will be part of the DCE – Connectivity Business Group, contributing to the development... for subsystems and IP blocks. Lead RTL development and integration, ensuring modularity, reusability, and compliance with design...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 12 Nov 2025

Digital IC design Engineer

Engineer with Marvell, you’ll be a member of the Custom compute and solutions group. Our design team works on state-of-the-art.... Implement designs using good RTL coding and low power techniques. Collaborate with the backend team to close on synthesis...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 08 Nov 2025
Salary: $121400 - 181800 per year

Digital, Mixed Signal IC Design Engineer, Principal

Engineer with Marvell, you’ll be a member of the Central Engineering business group. If you picture Marvell as a wheel, Central... other chip companies and big tech companies, familiar names to all candidates. What You Can Expect ASIC design engineer...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 07 Nov 2025
Salary: $146850 - 220000 per year

Integration Engineer

engineer to join our exciting team of problem solvers. Description The ideal candidate will have experience in ASIC design.... • RTL Integration: Manage and merge RTL codebases, ensure connectivity and bus/interface protocols (e.g., AMBA, AXI, AHB...

Company: Apple
Location: Santa Clara, CA
Posted Date: 07 Nov 2025
Salary: $126800 - 190900 per year

Testbench/Verification Engineer

The Role: Testbench/Verification Engineer for the Infinity Fabric team. The Fabric IP is a flexible and scalable high... and verification engineer with exceptional programming skills, System Verilog and UVM experience, proven experience with working...

Company: Managed Staffing
Location: Santa Clara, CA
Posted Date: 07 Nov 2025

Testbench/Verification Engineer

The Role: Testbench/Verification Engineer for the Infinity Fabric team. The Fabric IP is a flexible and scalable high... and verification engineer with exceptional programming skills, System Verilog and UVM experience, proven experience with working...

Company: Managed Staffing
Location: Santa Clara, CA
Posted Date: 06 Nov 2025

GPU Design Engineer - Memory Hierarchy

! Description As a GPU Design Engineer, you will participate in micro-architecture specification and RTL coding. Explore architecture trade...

Company: Apple
Location: Santa Clara, CA
Posted Date: 06 Nov 2025