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Keywords: RTL Design Engineer, Location: California

Page: 8

Standard Cell Design Methodology & Flow Engineer

to Design For Test, scan concept and write DFT friendly RTL Understands all aspects of implementation specification, design...Do you have passion to join a world-class Digital Design Engineering group and take imaginative and revolutionary ideas...

Company: Apple
Location: Santa Clara, CA
Posted Date: 16 Jul 2025

Digital Design Engineer - New College Grad

protocol Expertise/ understanding in digital designs RTL Exp Hands on experience with complete ASIC flow is required Good...

Company: Rambus
Location: San Jose, CA
Posted Date: 12 Sep 2025
Salary: $72200 - 134200 per year

Design Verification Lead

your career. THE ROLE: We are looking for an adaptive, self-motivative design verification engineer to join our growing team..., industry-leading technologies to market. You will participate in design verification methodology definition as well...

Posted Date: 09 Oct 2025

GPU Formal Design Verification

Job Title: GPU Formal Design Verification Position Description: Protingent Staffing has an exciting contract GPU... Formal Design Verification opportunity with our client located in San Jose, CA. Job Description: As a Formal Design...

Company: Protingent
Location: San Jose, CA
Posted Date: 25 Sep 2025
Salary: $50 - 60 per hour

DDr5 verification design ENG - Santa Clara, CA - AMDJP00004484

Hi Role : ASIC/RTL Design Engineer Location : Santa Clara, CA Contract THE ROLE: We are looking for an adaptive..., self-motivative Design Verification Engineer to join our growing team. As a key contributor, you will be part of a leading...

Company: Seneca Resources
Location: Santa Clara, CA
Posted Date: 19 Sep 2025

SOC Design - STA, Hardware Compute Group

of Echo devices is looking for a Senior SoC Design-STA Engineer to continue to innovate on behalf of our customers... knowledge of entire design process from Design specification, defining architecture, micro-architecture, RTL design...

Company: Amazon
Location: Sunnyvale, CA
Posted Date: 17 Sep 2025

Principal Networking ASIC Design Architect

_ THE ROLE: We are looking for a Fellow-level Engineer to join our team to develop world-class products around NICs.... In this role you will be engaged with NIC architects, micro architecture, RTL, CAD/Methodology, and internal stakeholders to define...

Posted Date: 16 Aug 2025

Wireless SOC Verification Engineer

of multi-chip SOC debug architecture. As a Design Verification Engineer on our team, you'll be at the center of the.... This position comes with responsibility for pre-silicon RTL verification of block and top-level SOC, all aspects of SOC Design...

Company: Apple
Location: Sunnyvale, CA
Posted Date: 12 Oct 2025

FPGA Engineer

. Proficiency in RTL design using Verilog or SystemVerilog. Proficiency in a scripting language such as Python, TCL, or Perl.... The silicon engineering team is at the heart of this innovation, and we are looking for a passionate FPGA Engineer to help...

Company: Apple
Location: Cupertino, CA
Posted Date: 12 Oct 2025

System Validation Engineer

Engineer to help us shape the next generation of the world's most advanced devices. As a key member of our team... and execute comprehensive tests to verify the functional integrity of our design on both FPGA prototyping platforms and final...

Company: Apple
Location: Cupertino, CA
Posted Date: 12 Oct 2025

Junior / Mid-level/ DSP Engineer - Commnuication Algorithm / MSEE / Irvine

development knowledge and experience and Ethernet PHY design - Sr. level Digital Signal Processing (DSP) R&D Engineer... verification with RTL simulations • Define and document chip requirements, architecture, verification and lab test plan Lab...

Location: Irvine, CA
Posted Date: 12 Oct 2025
Salary: $130000 - 180000 per year

FPGA Engineer

development phases of uArchitecture RTL Design-Physical Implementation-Timing Closure-Simulation Validation- Lab Based Silicon... Verilog RTL coding Experience in the design, test, delivery, support of multiple FPGAs shipping to customers Experience...

Company: Protingent
Location: Sunnyvale, CA
Posted Date: 11 Oct 2025
Salary: $50 - 80 per hour

Staff FPGA Engineer

, and functional verification. Collaborate with partners to finalize RTL design requirements. Develop RTL designs and build functional... States of America Job Description: Employer: Auris Health, Inc. Job Title: Staff FPGA Engineer Job Code: A011...

Location: Santa Clara, CA
Posted Date: 11 Oct 2025
Salary: $217000 - 240000 per year

ASIC Power Engineer

We are seeking an ASIC Power Engineer to drive SoC power simulation, analysis and optimization for next-generation... to achieve optimization goals. - Define comprehensive test cases within design verification environments. - Generate accurate pre...

Company: Apple
Location: Irvine, CA
Posted Date: 11 Oct 2025

SoC Power/Performance Post-Si Validation & Emulation Engineer

Summary: As a SoC Power/Performance Post-Si Validation & Emulation Engineer, you will be a vital member of our Global SoC... with IP teams to streamline RTL, ensuring compatibility, efficiency, and performance for various emulation platforms for power...

Company: Qualcomm
Location: San Diego, CA
Posted Date: 11 Oct 2025

Post-Silicon Validation Engineer

debug. Diagnose complex silicon issues across RTL, firmware, and hardware layers. Collaborate with design, verification...Post-Silicon Validation Engineer About Etched Etched is building AI chips that are hard-coded for individual model...

Company: Etched
Location: San Jose, CA
Posted Date: 11 Oct 2025

Sr. Staff Hardware Engineer - Hybrid

Experience with low-noise, high-efficiency, on-board power regulator design Experience with Verilog RTL Board-level debug... worldwide. Senior Staff Hardware engineer Gigamon is seeking a Sr. Staff Hardware Engineer to perform board-level circuit...

Company: Gigamon
Location: Santa Clara, CA
Posted Date: 11 Oct 2025

Emulation Engineer

for external customers. About the Role: The emulation engineer builds emulation and FPGA models and solutions from RTL design..., validation methodologies and tools Experience with RTL design, Verilog and simulation, debug tools such as Verdi, System Verilog...

Company: Intel
Location: Folsom, CA
Posted Date: 11 Oct 2025

ASIC Power Engineer

We are seeking an ASIC Power Engineer to drive SoC power simulation, analysis and optimization for next-generation... to achieve optimization goals. - Define comprehensive test cases within design verification environments. - Generate accurate pre...

Company: Apple
Location: Irvine, CA
Posted Date: 11 Oct 2025

Staff FPGA Engineer

, and functional verification. Collaborate with partners to finalize RTL design requirements. Develop RTL designs and build functional... of America Job Description: Employer: Auris Health, Inc. Job Title: Staff FPGA Engineer Job Code: A011...

Location: Santa Clara, CA
Posted Date: 10 Oct 2025
Salary: $217000 - 240000 per year