Principal Software Engineer (Verification of VIP using Verilog/SV/UVM )

. Job Description: Job Title: ( Verification of VIP using Verilog/SV/UVM – Ahmedabad ) Cadence is a pivotal leader in electronic design, building... of VIP using Verilog/SV/UVM – (Ahmedabad) CV to send K Madhu Prasad Job responsibilities: Responsible for verification...