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Keywords: Principal/ Senior Principal ASIC DFT Engineer, Location: USA

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Principal/ Senior Principal ASIC DFT Engineer

would be a plus Active Clearance or higher Senior Principal Engineer Basic Qualifications: Bachelor’s degree with 8 years of experience... and Responsibilities: Responsible for DFT (Design for Testabilty) aspects of ASIC Design thorough understanding of digital design...

Company: Northrop Grumman
Location: USA
Posted Date: 21 Nov 2025
Salary: $119600 - 179500 per year

Senior Principal DFT Design Engineer

. We are looking for SoC/ASIC Digital Design Engineer with experience in Design for Test (DFT). An intimate knowledge and experience in scan.... Requirements; US citizenship preferred. Prior 5-15 years of professional experience in SoC/ASIC Digital Design with focus...

Location: Austin, TX
Posted Date: 01 Nov 2025

Principal Engineer - Design For Test (DFT)

Principal Engineer with Marvell, you’ll be a member of the Custom Silicon Engineering team. This team is a leader in large multi... will be challenging and will require an experienced DFT engineer that can work with existing DFT solutions while also creating new...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 15 Nov 2025
Salary: $146850 - 220000 per year

Principal/ Senior Principal Digital ASIC Circuit Design Engineer

), SDC (Synopsys Design Constraints) Basic Qualifications for Sr. Principal Digital ASIC Circuit Design Engineer Level... to the warfighter. We are seeking a front-end ASIC design engineer for design and verification of full-custom digital...

Company: Northrop Grumman
Location: USA
Posted Date: 26 Nov 2025
Salary: $119600 - 179500 per year

Senior Principal ASIC Static Timing Engineer

. Northrop Grumman Mission Systems, Digital Technologies Group, is seeking a Static Timing Engineer to join our team of highly.../SystemVerilog) 4 years of experience in the full product life cycle of ASIC Design Preferred Qualifications: Master’s Degree...

Company: Northrop Grumman
Location: USA
Posted Date: 12 Nov 2025

Senior Principal Hardware Engineer

group designs and develops test platforms for validating multi-core Arm-based Network processors and custom ASIC’s, used... throughout the product development lifecycle. Work closely with manufacturing and test teams to ensure DFM/DFT compliance...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 07 Nov 2025
Salary: $164650 - 246700 per year

Senior Principal Digital IC Design Engineer

, accelerators, and subsystems. Work closely with the architecture, floor planning, backend, verification, DFT, STA teams... such as AXI, HBM, Ethernet, PCIe, and D2D. Experience in micro-architecture of complex custom/ASIC products, focusing...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 30 Oct 2025

Principal Technical IP Engineer - Manage 3rd Party IP Integration - DDR/LPDDR/GDDR/HBM/eMMC memory

, that is predominantly 3rd party IP. What You Can Expect Looking for a talented Principal Technical IP Engineer to join the Marvell Team..., above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As a Hardware Design Senior Staff...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 16 Nov 2025
Salary: $143200 - 214500 per year