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Keywords: Interconnect RTL Design Engineer, Location: Santa Clara, CA

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Principal Interconnect Micro-architect and RTL Design Engineer

and performance/power. In this role the candidate will work with IP and SOC Architecture team, RTL design team, verification team..., and physical design team to drive the RTL design and microarchitecture of modular network on chip IPs for AMD Data Center silicon...

Posted Date: 17 Dec 2025

Senior ASIC Physical Design Engineer, Cache Coherent Interconnects

expertise in high-frequency interconnect/cache/core design is preferred. Verilog expertise is preferred as is a deep... understanding of ASIC design flow including RTL design and verification, DFT, and ECO. Strong communication and interpersonal...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 21 Nov 2025

Senior ASIC/RTL Design Engineer

Job Description: Pay Range: $62.45hr - $78.78hr The ASIC/RTL Design Engineer Senior is responsible for designing... portions of design and implementation. XXgn and implement RTL blocks to meet functional, timing, area, and power requirements...

Company: Cynet Systems
Location: Santa Clara, CA
Posted Date: 25 Jan 2026
Salary: $62.45 - 78.78 per hour

Senior ASIC Design Engineer - Hardware

We are now looking for an ASIC Design Engineer. NVIDIA is seeking best-in-class ASIC Design Engineers to design...-architecture, implement in RTL, and deliver a fully verified, synthesis/timing clean design. Support post-silicon validation...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 24 Dec 2025

ASIC Design Engineer, GPU/ML Shader Core

your career. THE ROLE: We are looking for a ASIC Design Engineer, GPU/ML Shader Core who are motivated to challenge the status... for owning full design cycle from defining micro-architecture, implementing RTL, and deliver fully verified and PD timing clean...

Posted Date: 19 Dec 2025

GPU Design Engineer - Memory Hierarchy

! Description As a GPU Design Engineer, you will participate in micro-architecture specification and RTL coding. Explore architecture trade... in one or more areas of cache design, on-chip interconnect network, data compression or shader processor Ability to work well in a team...

Company: Apple
Location: Santa Clara, CA
Posted Date: 06 Nov 2025
Salary: $126800 - 190900 per year

GPU Design Engineer - Memory Hierarchy

! Description As a GPU Design Engineer, you will participate in micro-architecture specification and RTL coding. Explore architecture trade... help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You'll...

Company: Apple
Location: Santa Clara, CA
Posted Date: 06 Nov 2025

SOC Design Engineer

on developing the logic design, register transfer level (RTL) coding, integration, and simulation for AI System on Chips (SoCs... implementation. Key Responsibilities Develops the logic design, register transfer level (RTL) coding, simulation, and integrates...

Company: Intel
Location: Santa Clara, CA
Posted Date: 22 Jan 2026

Senior ASIC Design Engineer

design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO...NVIDIA is seeking best-in-class ASIC Design Engineers to design and implement the world’s leading SoC's and GPU...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 10 Dec 2025

ASIC Design Engineer - New College Grad 2026

and deliver high performance, area and power efficient RTL to achieve design targets and specifications. Analyze architectural... development (Verilog). Good understanding of ASIC design flow including RTL design, verification, logic synthesis and timing...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 19 Nov 2025
Salary: $96000 - 161000 per year

Testbench/Verification Engineer - Santa Clara, CA, or Boxborough, MA, or Austin, TX

Testbench/Verification Engineer 6 Months The location can be Santa Clara (preferrable), or Boxborough... debug - Scripting language (Perl, Python, Ruby - Proven experience in debugging the test-bench, VIP, RTL code NICE...

Company: Sunrise Systems
Location: Santa Clara, CA
Posted Date: 10 Jan 2026

Senior SoC Performance Architect

for server-class SoCs, correlate models against RTL behavior, prototype ideas and help productize performance/power features... for future SoC designs. Minimum Skill sets: MS in Computer Science/Computer Engineering/Electrical Engineer with 3 years...

Company: Qualcomm
Location: Santa Clara, CA
Posted Date: 18 Jan 2026