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Keywords: IP/Subsystem Verification Lead, Location: Bangalore, Karnataka

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IP/Subsystem Verification Lead

include IP and subsystem design verification and working collaboratively with the IP/SoC team. Key Responsibilities... bring to life cutting-edge designs. You will lead a front-end design verification team, and work closely with architecture...

Posted Date: 30 Aug 2025

IP/Subsystems Design Verification Lead

specifications. Responsibilities include IP and subsystem design verification and working collaboratively with the IP/SoC team. Key... with architecture, IP design and SOC verification engineers to achieve first pass silicon success. Design Verification Engineer The...

Posted Date: 10 Aug 2025

Lead RTL integration Engineer - IP/subsystems

include IP and subsystem design, integrating multiple IPs, performing quality checks and working collaboratively with the IP... of the IP team to support design verification, implementation (synthesis, constraints, static timing analysis), and delivery...

Posted Date: 13 Aug 2025

IP Design Verification Lead

of technical ownership and execution to drive block level IP and/or MP subsystem design and verification assignments to completion... and maintain block level IP and MP subsystem verification architecture, testbenches, test methodology and infrastructure Develop...

Posted Date: 04 Sep 2025

IP Verification Lead

Proficient in SubSystem level ASIC verification * Architected and developed complex verification environments and infrastructure..._ MTS SILICON DESIGN ENGINEER THE ROLE: The Infinity Fabric transport layer verification team...

Posted Date: 19 Aug 2025

IP Verification Lead

Proficient in SubSystem level ASIC verification * Architected and developed complex verification environments and infrastructure..._ MTS SILICON DESIGN ENGINEER THE ROLE: The Infinity Fabric transport layer verification team...

Posted Date: 14 Aug 2025

Senior Lead Verification Engineer

Job Requirements The ideal candidate for this Senior Lead Verification Engineer position... should have a strong background in verification methodologies and be able to effectively lead a team in achieving project goals.9-10 Yrs of work...

Company: Quest Global
Posted Date: 13 Aug 2025

Techincal Lead- Design Verification

Job Requirements The ideal candidate for this Senior Lead Verification Engineer position... should have a strong background in verification methodologies and be able to effectively lead a team in achieving project goals. 10-12 Yrs of work...

Company: Quest Global
Posted Date: 13 Aug 2025

DSP / NPU Senior Lead Design Verification Engineer

verification of complex Qualcomm propriety DSP/NPU IP · DSP team is responsible for delivering high-performance DSP/NPU cores... from chipsets and royalties from intellectual property. Job Responsibilities: · Drive design verification of DSP IP by working...

Company: Qualcomm
Posted Date: 10 Sep 2025

RTL Design Lead - IP Design

cutting-edge designs. You will lead a front-end design and integration team, working closely with the architecture, IP design... IP and subsystem design, integrating multiple IPs, performing quality checks and working collaboratively with the IP/SoC...

Posted Date: 24 Aug 2025

Design Verification Sr Staff Engineer

–10 years of relevant experience - Strong background in IP, Subsystem and SoC verification, including methodology.../Career solutions including the CXL product line. What You Can Expect Develop and maintain testbenches for IP, subsystem...

Company: Marvell
Posted Date: 20 Sep 2025

Design Verification Senior Principal Engineer

of relevant experience - Strong background in IP, Subsystem and SoC verification, including methodology and testbench development..., above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact - Be part of the Design Verification...

Company: Marvell
Posted Date: 20 Sep 2025

Sr. SOC level verification -GDP (PCIE,USB,Ethernet ) Engineer

) Expertise in IP, Subsystem and SOC Verification with specialization in Integration, verification tools Strong hands... for GDP (PCIE,USB,Ethernet,I2C,I3C,Uart,SPI) and subsystem or signature IP’s in the complex SOC. He will be responsible...

Posted Date: 09 Sep 2025

Design Verification Senior Staff Engineer

–10 years of relevant experience - Strong background in IP, Subsystem and SoC verification, including methodology.../Career solutions including the CXL product line. What You Can Expect Develop and maintain testbenches for IP, subsystem...

Company: Marvell
Posted Date: 05 Sep 2025

Senior Manager, Design Verification Engineering

and execute verification test plan for IP, Block, Subsystem, and ARM-based SOC using System Verilog/UVM methodology and C-based... Design Verification team at Aeva India, you will build and lead a team of talented verification engineers to verify new...

Company: Aeva
Posted Date: 30 Jul 2025

Design Verification Senior Principal Engineer

with IP, Subsystem, and SoC teams on test plan creation, testbench architecture, and milestone reviews · Work closely... with Design and DV teams across IP, Subsystem, and SoC levels for test plan - development, execution, debug, coverage closure...

Company: Marvell
Posted Date: 26 Jul 2025

Design Verification Senior Principal Engineer

with IP, Subsystem, and SoC teams on test plan creation, testbench architecture, and milestone reviews · Work closely... with Design and DV teams across IP, Subsystem, and SoC levels for test plan - development, execution, debug, coverage closure...

Company: Marvell
Posted Date: 06 Jul 2025

Digital Design Lead

state of the art. About the Role As SOC Design Lead one will be responsible for driving complex SOC project... to define hardware architecture, work with verification team for pre silicon verification, DFT and Physical design team for SOC...

Posted Date: 20 Sep 2025

Lead I - Embedded Software

for simulation and Emulation/FPGA platform Experience with System Verilog IP/Subsystem and SOC development environment Knowledge... debugging integrating firmware/ applications and development level testing of complex SW/HW systems. Work directly with IP...

Company: UST
Posted Date: 28 Aug 2025

Lead I - Embedded Software

for simulation and Emulation/FPGA platform Experience with System Verilog IP/Subsystem and SOC development environment Knowledge... debugging integrating firmware/ applications and development level testing of complex SW/HW systems. Work directly with IP...

Company: UST
Posted Date: 28 Aug 2025