We are looking for passionate and motivated PCIE Gen6/CXL 3.0 IP/Subsystem Design Verification Engineers to work on PCIE/CXL based Memory Pooling... with hands-on knowledge in SV/UVM Strong Working experience in PCIE Gen6/CXL3.0 Familiarity with standard verification tools...
/Career solutions including the CXL product line. What You Can Expect Job Responsibilities: · Lead End-to-End SoC DV... with Design and DV teams across IP, Subsystem, and SoC levels for test plan - development, execution, debug, coverage closure...
/Career solutions including the CXL product line. What You Can Expect Job Responsibilities: · Lead End-to-End SoC DV... with Design and DV teams across IP, Subsystem, and SoC levels for test plan - development, execution, debug, coverage closure...