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Keywords: DFT Lead - Design for Test - ATPG, Location: Bangalore, Karnataka

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DFT Lead - Design for Test - ATPG

EXPERIENCE: Understanding of Design for Test methodologies and DFT verification experience (eg. IEEE1500, JTAG 1149.x, Scan... and features Scan insertion and ATPG pattern generation ATPG patterns verification with gate-level simulation Test coverage...

Posted Date: 05 Dec 2025

SOC DFT & Test Manager

on building robust DFT architectures—including ATPG, MBIST, LBIST, analog and boundary scan test—and extending them into efficient.... Your Job: Lead, mentor, and manage the DFT and post-silicon test engineering team, overseeing technical direction, execution...

Posted Date: 05 Dec 2025

DFT CAD Engineer, Sr Lead

is looking for DFT/ATPG Methodology development lead to develop DFTCAD methodologies for Qualcomm's 5G products in advanced FinFET... Responsibilities Lead DFT ATPG flow development, integration, and deployment efforts independently, collaborating with DFT teams, EDA...

Company: Qualcomm
Posted Date: 04 Dec 2025

DFT (DFX) Lead Engg

, and be able to independently drive tasks to completion. Key Responsiblities Lead and define PHY specific Design for Test... your career. SMTS SILICON DESIGN ENGINEER THE ROLE: Circuit Technology team is looking for a passionate and experienced DFT...

Posted Date: 14 Nov 2025

DFT Engineer

quicker on the most trusted hardware platform in today's market. We are looking for a DFT lead to join our dynamic team... and drive excellence in chip test strategies, design and testability. Your role and responsibilities We are seeking highly...

Company: IBM
Posted Date: 12 Dec 2025

Senior DFT Engineer

architecture definition Understand SoC architecture and test requirements. Work very closely with the lead Product/Test... engineering throughout the DFT definition phase to determine efficient ways to optimize test cost and achieve high test coverage...

Posted Date: 12 Dec 2025

Staff Engineer - ASIC Development Engineering (DFT)

to integrate DFT solutions into the overall ASIC design flow Develop and optimize test patterns using Automatic Test Pattern... coverage, fault coverage, and test time for ASIC designs Troubleshoot and debug DFT-related issues during the design and post...

Company: SanDisk
Posted Date: 04 Dec 2025

Staff Engineer, DFT Engineering

Test Pattern Generation (ATPG) DFT Rule Checks (DFT DRC) Scan chain compression and stitching Low-power DFT..., ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at and on and . We are seeking a SoC DFT Lead...

Posted Date: 04 Dec 2025

Staff/ Senior Staff DFT Engineer

organization. Influence design architecture decisions by providing early DFT input to maximize test coverage and minimize silicon... development, EDA/methodology development and IP/Chip design development. India DFT team is a key part of Global DFT community...

Company: Marvell
Posted Date: 22 Nov 2025

DFT (RTL) Engineer

your career. MTS SILICON DESIGN ENGINEER THE ROLE: We are seeking a highly experienced DFT (Design for Test) MTS... team around you. KEY RESPONSIBILITIES: Develop and Optimize Test Architectures Design and implement advanced test...

Posted Date: 22 Nov 2025

Senior DFT Engineer

your career. SMTS SILICON DESIGN ENGINEER THE ROLE: We are seeking a highly experienced DFT (Design for Test) Senior MTS... to integrate DFT requirements seamlessly into the overall design process. Lead Cross-Site Collaboration Coordinate with teams...

Posted Date: 22 Nov 2025

Senior DFT Engineer, SSG

. Make history. We are seeking a seasoned and strategic Sr DFT Engineer to Lead end-to-end Design-for-Test (DFT) planning... logic design. ATE Test Readiness: Lead DFT-to-ATE handoff, including: Drive generation and sign-off of high-quality test...

Company: Amazon
Posted Date: 25 Oct 2025

Associate II - VLSI DFT

and analysis is a plus. Understanding of test compression and ATE debug is a plus. Skills: DFT,Mbist,Subsystem design... of VLSI Frontend Backend or Analog design under minimal supervison from the Lead Outcomes: * As an Individual contributor...

Company: UST
Posted Date: 13 Oct 2025

Associate II - VLSI DFTN

and analysis is a plus. Understanding of test compression and ATE debug is a plus. Skills: DFT,Mbist,Subsystem design... of VLSI Frontend Backend or Analog design under minimal supervison from the Lead Outcomes: * As an Individual contributor...

Company: UST
Posted Date: 14 Oct 2025