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Keywords: DFT Engineer, Location: San Jose, CA

Page: 1

ASIC DFT Engineer

Broadcom is seeking candidates for a Staff DFT engineer position. The successful candidate will be responsible... for test. Responsibilities Own IP DFT architecture, implementation, verification, signoff STA constraints for DFT...

Company: Broadcom
Location: San Jose, CA
Posted Date: 05 Feb 2026
Salary: $120000 - 192000 per year

Staff DFT Engineer

We are looking for a staff DFT engineer with expertise in DFT and associated domains and skills in the following areas.... · Knowledge of latest state-of-the-art trends in DFT, test and silicon engineering. · Hands-on experience with JTAG standards...

Company: Broadcom
Location: San Jose, CA
Posted Date: 28 Nov 2025

DFT Engineer

Broadcom’s CSG division is seeking candidate for a DFT lead position. The successful candidate will be responsible... for leading most complex and cutting edge network switching ASIC DFx (Design for Test/debug & manufacturability) from DFT...

Company: Broadcom
Location: San Jose, CA
Posted Date: 20 Nov 2025
Salary: $120000 - 192000 per year

Principal Test Engineer

an exceptional Principal Test Engineer to join our Operations team in San Jose. In this role, you will be working with some of the... coverage and DFT (Scan/ATPG/JTAG/BIST). Experience working with Local and offshore OSAT's. Experience and in-depth knowledge...

Company: Rambus
Location: San Jose, CA
Posted Date: 14 Feb 2026

ASIC/SoC Design Engineer, RTL design for SoC IPs

your career. ASIC DESIGN ENGINEER THE ROLE: Join AMD's Silicon Design team to design and develop cutting-edge IPs... for next-generation embedded products. As a Senior ASIC Design Engineer, you will own the complete RTL design lifecycle from micro...

Posted Date: 12 Feb 2026

Principal Test Engineer - 93k Exp Required

Overview . Principal Test Engineer – 93k Exp Req Lead the Future of High-Speed, Secure Silicon at Rambus... Experience and in-depth knowledge of Advantest V93k required Experience with Test coverage and DFT (Scan/ATPG/JTAG...

Company: Rambus
Location: San Jose, CA
Posted Date: 12 Feb 2026

Technical Staff Engineer - Architecture (SOC)

! Job Description Job Description: Join our dynamic FPGA (Field Programmable Gate Array) Business Unit as a Technical Staff SOC Architecture Engineer. We are at the... with Logic Verification and ASIC Implementation teams through synthesis and DFT insertion. Lead discussions with CPU and IP...

Company: Microchip
Location: San Jose, CA
Posted Date: 11 Feb 2026

Senior Technical Staff Engineer - Design for Test

/External/job/Senior-Technical-Staff-Engineer---Architect--DFT-Lead-_R430-26-1 The DFT lead works in close partnership..., and test engineering to implement the testability features into the combined FPGA and ASIC SOC. The DFT lead will be involved...

Company: Microchip
Location: San Jose, CA
Posted Date: 11 Feb 2026

Hardware Engineer (Onsite)

. Your Impact Act as a Product Test Engineer in Silicon Operations Quality and Reliability team who will partner with NPI Product... Test Engineering teams, DFT, and Design Engineering to define and run ATE and CFT testing for qualification and reliability...

Company: Cisco Systems
Location: San Jose, CA
Posted Date: 11 Feb 2026

Hardware Engineer (Onsite)

. Your Impact Act as a Product Test Engineer in Silicon Operations Quality and Reliability team who will partner with NPI Product... Test Engineering teams, DFT, and Design Engineering to define and run ATE and CFT testing for qualification and reliability...

Company: Cisco Systems
Location: San Jose, CA
Posted Date: 11 Feb 2026

Sr Principal Test Engineer

Overview Sr. Principal Test Engineer – 93k Exp Req Lead the Future of High-Speed, Secure Silicon at Rambus... Experience and in-depth knowledge of Advantest V93k required Experience with Test coverage and DFT (Scan/ATPG/JTAG...

Company: Rambus
Location: San Jose, CA
Posted Date: 11 Feb 2026

Senior SoC RTL Design Engineer (remote)

Senior RTL Design Engineer Remote / work from any US location MUST be a US Citizen or US Permanent Resident Full... implementation Resolve Lint, CDC, and DFT related issues Required Skills & Experience: BSEE/MSEE with 10+ years of SoC design...

Location: San Jose, CA
Posted Date: 11 Feb 2026

ASIC/SoC Design Engineer, RTL design for SoC IPs

your career. ASIC DESIGN ENGINEER THE ROLE: Join AMD's Silicon Design team to design and develop cutting-edge IPs... for next-generation embedded products. As a Senior ASIC Design Engineer, you will own the complete RTL design lifecycle from micro...

Posted Date: 08 Feb 2026

Principal Mechanical Engineer- Video Collaboration

Mechanical Engineer to be a senior technical leader and decision-maker on our Video Collaboration product development team.../DFT, tooling development, pilot builds, and production ramp. Bridge time zones and cultures, communicating effectively...

Company: Logitech
Location: San Jose, CA
Posted Date: 06 Feb 2026

System Test Engineer (Hybrid)

, CA. We are seeking a dedicated and proactive System Quality & Manufacturing Test Engineer to champion quality-focused support... health dashboards. Knowledge of Design for Manufacturing (DFM) or Design for Test (DFT), and test planning for high...

Company: Cisco Systems
Location: San Jose, CA
Posted Date: 05 Feb 2026
Salary: $135800 - 193400 per year

RF/HW Test Engineer

Validation, DFT, RTL-to-GDSII, Physical Design, Mask Layout, and Silicon Bring-up. Our embedded services span firmware, device...+ countries. Prodapt is looking for a RF/HW Test Engineer (contract) to support RF and hardware validation across both prototype...

Company: Prodapt
Location: San Jose, CA
Posted Date: 05 Feb 2026

RF/HW Test Engineer

Verification, Emulation, FPGA Validation, DFT, RTL-to-GDSII, Physical Design, Mask Layout, and Silicon Bring-up. Our embedded... with over 6,000 experts in 30+ countries. Prodapt is looking for a RF/HW Test Engineer (contract) to support RF and hardware...

Company: Prodapt
Location: San Jose, CA
Posted Date: 04 Feb 2026

Application Engineer

Job Description: Job Description: As an Application Engineer, you will be working with a dynamic team to provide... Experience in coaching team members and Advantest customers Experience with SSN, PCIe. Understanding of DFT (Design for Test...

Company: Advantest
Location: San Jose, CA
Posted Date: 04 Feb 2026

Associate Engineer, Physical Design Engineering

of What's Possible™. Learn more at and on and . About the Role We are seeking a New College Graduate Physical Design Engineer... in Physical Design or ASIC implementation. Exposure to timing ECO, low-power design (UPF), and DFT integration. Understanding...

Company: Analog Devices
Location: San Jose, CA
Posted Date: 03 Feb 2026
Salary: $86043 - 118309 per year

Senior Staff Yield & Product Engineer

's technology. As a Senior Staff Yield & Product Engineer in our Research & Development team, you'll have the opportunity to merge... Improvement, Test-time Reduction, RMA Support, Sustaining, and Manufacturability Partner with Design, DFT/DFM, Process, Packaging...

Company: Infineon
Location: San Jose, CA
Posted Date: 31 Jan 2026