to 12 years of experience in ASIC Verification Engineering Demonstrated experience in the use of System Verilog... one or more architectural functional blocks using a combination of simulation, formal, and coverage methods. Develop verification, functional...
for designer testing of code, debugging code during simulation and regression verification Assist the verification team... if applicable Report on status updates on a regular basis 8 to 12 years of experience in ASIC design engineering Proficiency...
products. What You Can Expect ASIC design engineer responsible for the design, verification and evaluation of digital... in digital logic design Understand ASIC verification flows and methodologies Verilog, SystemVerilog, UVM UNIX Shell scripting...