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Keywords: ASIC Physical Design and Timing Engineer, Location: Santa Clara, CA

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ASIC Physical Design and Timing Engineer

, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic.... What you'll be doing: Drive Physical Design and timing analysis and closure of NVIDIA's GPUs, CPUs, DPUs and SoCs at block level...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 21 Sep 2025
Salary: $108000 - 184000 per year

CPU Server Physical Design Timing Engineer

Design Timing Engineer, you will work with microarchitecture and RTL design team to develop timing constraints, drive...: In this role you will have the opportunity to define, develop and drive CPU timing closure for Oryon CPU Cores. As a CPU Physical...

Company: Qualcomm
Location: Santa Clara, CA
Posted Date: 25 Jul 2025

Sr. Staff Static Timing Analysis (STA) Engineer

Physical Design team at Marvell in Santa Clara is seeking a Sr. Staff Static Timing Analysis (STA) Engineer to contribute... physical design strategies, methodologies and deep sub-micron technology issues like N5/N3/N2. Familiar with ASIC design flow...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 27 Sep 2025
Salary: $124420 - 186400 per year

Senior Timing Methodology Engineer

, self-heating, thermal impact, IR drop etc. Collaborate with technology leads, VLSI physical design, and timing engineers... To See: MS (or equivalent experience) in Electrical or Computer Engineering with 3 years’ experience in ASIC Design and Timing...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 20 Jul 2025

ASIC Clocks Design Engineer - New College Grad 2025

of timing closure to innovate and implement new Clocking topologies in RTL. Collaborate with Physical design and timing team... ASIC engineer to join the team. The Team is responsible for crafting all aspects of GPU and CPU clocking. The team...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 28 Sep 2025
Salary: $108000 - 184000 per year

Senior ASIC Design Engineer - Circuits

We are now looking for a motivated Senior ASIC Design Engineer to join our dynamic and growing team in our Circuit... with all stages of ASIC design flow including front end design and verification, DFT, and timing analysis Strong team player...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 27 Aug 2025

Senior ASIC Design Engineer – Clocks IP

of timing closure to innovate and implement new Clocking topologies in RTL. Collaborate with Physical design and timing team... ASIC engineer to join the team. The Team is responsible for crafting all aspects of GPU and CPU clocking. The team...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 31 Jul 2025

Senior ASIC Design Engineer

NVIDIA is seeking an outstanding Senior ASIC Design Engineer to design and implement the world’s leading SoC's and GPU... with verification engineers. Deliver a synthesis/timing clean design while working with the physical design team to ensure a routable...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 31 Jul 2025

Senior ASIC/RTL Design Engineer

, emulation, debug, synthesis, and timing closure, interfacing with physical execution, software, and silicon bring-up teams.... Experience and Education: SoC XXgn. Knowledge AND hands-on experience from industry ASIC design flow, including RTL coding, IP...

Company: Cynet Systems
Location: Santa Clara, CA
Posted Date: 24 Sep 2025
Salary: $70.86 - 75.86 per hour

Principal Networking ASIC Design Architect

and deploy end to end power optimization methodology for Physical Design Implementation Define PVT corners, device frequency... and strong collaboration across multiple business units PREFERRED EXPERIENCE: Deep experience in physical design and methodology preferred...

Posted Date: 17 Aug 2025

Senior Reset and Boot ASIC Engineer

NVIDIA is looking for a Senior Reset and Boot ASIC Engineer to join our System ASIC team! NVIDIA has continuously.... What you’ll be doing: Be an integral part of the System ASIC Design team to help with the Micro-architecture definition...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 30 Sep 2025

ASIC Implementation Engineer - PnR & FE

. Experience with SOC design integration and Front-end implementation. Knowledge of Timing/physical libraries and memories... a highly motivated and experienced ASIC Implementation Engineer to join our dynamic team. The ideal candidate...

Posted Date: 04 Sep 2025

GPU Top Level Physical Design Engineer

Physical Design engineer, you will collaborate with FE team to understand RTL and drive physical aspects early in design cycle...) Preferred Qualifications Experience with hierarchical design approach, top-down design, budgeting, timing and physical...

Company: Apple
Location: Santa Clara, CA
Posted Date: 12 Sep 2025

Senior Logic Design Engineer– Physical Design

We are now looking for a Logic Design Engineer with Physical Design background! As a member of our CPU Logic Design... with the physical design team on implementation, synthesis and timing closure as well as working on micro-architectural...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 11 Sep 2025

GPU Physical Design Engineer

route and placement flow experiments, reviewing static timing, and physical design verification flow results. Preferred... with hierarchical design approach, top-down design, budgeting, timing, and physical convergence will be an asset. Experience...

Company: Apple
Location: Santa Clara, CA
Posted Date: 17 Jul 2025

Sr. Silicon Design Engineer

_ Job Role and Responsibility: AMD, Inc. is hiring a Sr. Silicon Design Engineer to research, design, develop, and/or test.... Perform definition, design, verification, and/or documentation for ASIC development. Determine architecture design, logic...

Posted Date: 21 Sep 2025

Sr. Silicon Design Engineer

_ Job Role and Responsibility: AMD, Inc., is hiring Sr. Silicon Design Engineer to Research, design, develop, and/or test.... Oversee definition, design, verification, and/or documentation for ASIC development. Determine architecture design, logic...

Posted Date: 21 Sep 2025

Sr. Silicon Design Engineer

++, or Python: ASIC design tools (synthesis, simulation, equivalence checking, or static timing analysis); and Design flows..._ Job Role and Responsibility: AMD, Inc., is hiring Sr. Silicon Design Engineer to Research, design, develop, and/or test...

Posted Date: 21 Sep 2025

MTS Silicon Design Engineer

. Oversee definition, design, verification, and/or documentation for ASIC development. Determine architecture design, logic... Architects, RTL writers, and Physical Design engineers. Evaluate all aspects of the process flow from high-level designs...

Posted Date: 21 Sep 2025

Principal Silicon Design Engineer

design team and physical design team for large scale ASIC chip physical implementation Drive design and methodology... Timing closure for high-speed designs. CDC, PTPX, STA, LINT & DFT, IP, Physical design flow & scripting in TCL, Python...

Posted Date: 20 Sep 2025