Find your dream job now!

Click on Location links to filter by Job Title & Location.
Click on Company links to filter by Company & Location.
For exact match, enclose search terms in "double quotes".

Keywords: ASIC Design Engineer || RTL Design/Front-end/Lint/CDC || Exp 7 to 10 years, Location: Bangalore, Karnataka

Page: 1

ASIC Design Engineer || RTL Design/Front-end/Lint/CDC || Exp 7 to 10 years

: specification, RTL design, lint, cdc, timing analysis, formal verification, system testing. Validated experience in flow automation.... You will have an ASIC design background with hands-on experience in RTL design with in-depth knowledge of ASIC/SoC development cycle, the...

Company: Splunk
Posted Date: 29 Jan 2026

Modem design/RTL (Sr Staff)

required The candidate must have at least 10 years of front-end ASIC RTL design experience. The candidate must be strong in design... of industry-standard front-end tool flows (lint, CDC, etc.). Strong critical thinking, problem-solving, and debugging skills...

Company: Qualcomm
Posted Date: 05 Nov 2025

Staff Digital Design Engineer

(or equivalent) 7+ years of experience in ASIC/SoC digital design Proficiency with front-end digital design and scripting..., measure, and connect. The Position Analog Devices is seeking a staff digital design engineer for its Data Center & Energy...

Posted Date: 21 Jan 2026

Staff DFT Engineer

skills using Perl, Tcl, and/or Python. Solid understanding of digital design fundamentals, including RTL design, Lint/CDC..., MBIST, boundary scan, and test access strategies Drive testability requirements early in the RTL design phase Balance...

Posted Date: 28 Jan 2026

Security & Access Control Engineer/Lead

's or Master's degree in Computer Engineering, Electrical Engineering, or related field. 7-10+ years of experience in security... and virtualization technologies. OS and hypervisor security. Programming skills in C/C++, Python; familiarity with RTL design...

Company: Qualcomm
Posted Date: 18 Dec 2025

Staff Engineer, DFT Engineering

understanding of digital design fundamentals, including RTL design, Lint/CDC, low power checks, and the full ASIC design flow...’s degree in Electrical/Electronics Engineering or a closely related field. 7+ years of hands-on experience in DFT...

Posted Date: 04 Dec 2025

Senior Physical Verification Engineer

field. 5–10+ years of experience in ASIC/SoC physical verification, with proven ownership of block and/or full‑chip signoff... Verification Engineer is responsible for full‑chip and block‑level signoff of advanced ASIC/SoC designs, ensuring manufacturability...

Posted Date: 12 Dec 2025