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Keywords: Verification Engineer - UVM / ASIC, Location: Santa Clara, CA

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GPU Design Verification Engineer

and strong programming skills in System Verilog, OVM and UVM Hands on verification experience working on ASIC, CPU or GPU Test Plan...Job Details: Job Description: Performs functional verification of graphics logic components, including 3D graphics...

Company: Intel
Location: Santa Clara, CA
Posted Date: 15 Feb 2026

Design Verification Engineer

understanding of complex/random System Verilog/UVM verification environments Write and execute test cases Debug failures... company, etc. What You Can Expect Work on verification of Marvell's AI/ML, Network Processing, Compute, Memory Expander...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 07 Feb 2026
Salary: $96570 - 144600 per year

Silicon Engineer

in UVM/C verification methodology. 2+ years of experience with functional validation of complex ASIC SOC. Knowledge...Lead key components of functional validation of complex ASIC SOC using UVM/C test bench Perform pre-silicon SoC...

Company: Microsoft
Location: Santa Clara, CA
Posted Date: 22 Feb 2026

Applications Engineering Consultant – FPGA Prototyping

team out of the Fremont office. As an FPGA Prototyping Applications Engineer, you will contribute to our success... by assisting in the sales and deployment of Siemens FPGA Prototyping verification products as well as by increasing customer...

Company: Siemens
Location: Santa Clara, CA
Posted Date: 15 Feb 2026