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Keywords: Verification Engineer, Low Power, Location: Bangalore, Karnataka

Page: 7

DV Technical Manager

Job Requirements Job Description Job Title: Senior Gate-Level Simulation (GLS) Verification Engineer Location... skilled and meticulous Gate-Level Simulation (GLS) Verification Engineer to serve as the last line of defense before silicon...

Company: Quest Global
Posted Date: 12 Nov 2025

RTL / Soc Design & Integration Lead

Low power digital design and analysis Modern SOC tools including Spyglass, Questa CDC, Cadence Conformal, VCS simulation... design teams. Strong understanding of SOC globals like clocking, reset, boot and power management flows, low power design...

Posted Date: 29 Oct 2025

Digital Design Engineering

functional GLS verification would be an advantage but is not necessary. The design engineer in ADI is encouraged to participate... experience is a must including high-speed and low-power(UPF) RTL design. Work experience in Ethernet domain is highly desired...

Posted Date: 24 Oct 2025

DV SV UVM

-related issues. Knowledge of low-power verification techniques (UPF). Prior experience contributing to post-silicon.... Experience with Gate-Level Simulations (GLS) and debugging timing-related issues. Knowledge of low-power verification techniques...

Company: Quest Global
Posted Date: 23 Oct 2025

Associate II - VLSI DFT

style DFT architectures including multi-clock domain and low power design practices. - Knowledge of DFT including Scan..., MBIST - Knowledge of low power design methodology (static/dynamic clock gating, power gating, dynamic voltage and frequency...

Company: UST
Posted Date: 14 Oct 2025

Associate II - VLSI DFTN

style DFT architectures including multi-clock domain and low power design practices. - Knowledge of DFT including Scan..., MBIST - Knowledge of low power design methodology (static/dynamic clock gating, power gating, dynamic voltage and frequency...

Company: UST
Posted Date: 14 Oct 2025

SV UVM

. Experience with Gate-Level Simulations (GLS) and debugging timing-related issues. Knowledge of low-power verification techniques...Job Requirements Design Verification Engineer Job Description Job Summary We are seeking a talented and detail...

Company: Quest Global
Posted Date: 27 Sep 2025

DV Coresight_JTAG

& Verification: Integrate debug and trace IP with the main SoC fabric, ensuring correct connectivity, clocking, and power domain...Job Requirements About the Role We are seeking a skilled and experienced Hardware/Firmware Engineer...

Company: Quest Global
Posted Date: 27 Sep 2025

Lead Full Chip timing, STA Expertise

knowledge is expected. STA closure/convergence execution on Low power designs is an added advantage. Expertise in industry..._ PMTS SILICON DESIGN ENGINEER THE ROLE: The position will involve working with a very experienced physical design team...

Posted Date: 20 Sep 2025

SV UVM

. Experience with Gate-Level Simulations (GLS) and debugging timing-related issues. Knowledge of low-power verification techniques...Job Requirements Design Verification Engineer Job Description Job Summary We are seeking a talented and detail...

Company: Quest Global
Posted Date: 17 Sep 2025