with evidence. Deep understanding of HR operations and organizational structures;some background in tech industry HR environments...
Design and develop Soft IP for FPGAs using Verilog/SystemVerilog Integrate third-party IP cores into FPGA systems with custom RTL wrappers Collaborate with verification teams to debug and validate IP functionality Support board bring-...
Develop and implement the verification plan for complex ASIC/SOC blocks. Architect, build, and maintain the UVM testbench environment. Create and execute test cases to validate functionality and performance. Perform code and functiona...
Job Title: ASIC/RTL Design Engineer Duration: 12+ months Location: Santa Clara, CA Key Responsibilities: Develop/Maintain tests for functional verification. Build the directed and random verification tests, debug test failures to det...
Job Title: Performance Modeling Engineer Location: Santa Clara, CA (Remote Possible) Duration: 12+ months (Possible Extension-Long Term Project) Note: SystemC/TLM2 is must Description: Develop, enhance, and maintain SystemC/TLM2 model...