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Keywords: System IP Design Verification Engineer, Location: San Jose, CA

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Post-Silicon Validation Engineer

debug. Diagnose complex silicon issues across RTL, firmware, and hardware layers. Collaborate with design, verification...Post-Silicon Validation Engineer About Etched Etched is building AI chips that are hard-coded for individual model...

Company: Etched
Location: San Jose, CA
Posted Date: 11 Oct 2025

Principal Software Development Engineer

, and verification skills along with proficiency in design/code reviews and writing automated unit and integration tests.... We are hiring a Principal Software Development Engineer to join our Central Authority team. You will work on the control plane...

Company: Zscaler
Location: San Jose, CA
Posted Date: 01 Oct 2025

Strategic Sourcing Engineer, Silicon

solutions to determine the best fit for internal design requirements (EDA, Chiplet, IP Evaluation) Evaluate processor cores... and resolve issues related to EDA, IP and chiplets during various stages of the design cycle Act as the primary point of contact...

Company: Groq
Location: San Jose, CA
Posted Date: 26 Sep 2025

Sr Principal Analog Test & Characterization Engineer

team to debug and characterize the mixed signal IP test chips and ASICs. Write and support design engineers to create test... design team! Here you'll have the chance to play an important role in terms of validating and characterizing the top-notch...

Company: Nokia
Location: San Jose, CA
Posted Date: 16 Oct 2025

FPGA/ASIC Engineer

methodology. Option to engage in block-level RTL design or block or top-level IP integration. Collaborate with Software, Design...-million gate SoC designs onto prototyping platforms, creating design partitions, FPGA builds, and testbenches to simulate FPGA...

Company: Nesco Resource
Location: San Jose, CA
Posted Date: 18 Sep 2025
Salary: $60 - 65.33 per hour