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Keywords: Synopsys, Location: Canada

Page: 3

Analog Design Co-op

from MathWorks, Cadence, Mentor and Synopsys for analog design (eg Matlab, Virtuoso, Calibre, STAR-RC, MMSIM). Assets...

Company: Ciena
Location: Ottawa, ON
Posted Date: 30 Jan 2026

Physical Design Engineer - Flow & Methodology

, power/IR analysis, and physical verification). Proficiency with Synopsys, Cadence, and/or Siemens EDA tools...

Location: Markham, ON
Posted Date: 26 Jan 2026

Physical Design Engineer - Flow & Methodology

, power/IR analysis, and physical verification). Proficiency with Synopsys, Cadence, and/or Siemens EDA tools...

Location: Markham, ON
Posted Date: 25 Jan 2026

Senior AI/ML ASIC Design Verification (Formal) Engineer

, and coverage. Experience using at least one formal verification tool, such as Synopsys VC Formal, Cadence JasperGold, or Siemens...

Company: Qualcomm
Location: Markham, ON
Posted Date: 24 Jan 2026
Salary: $104900 - 154900 per year

Silicon Design Engineer

: Python, Tcl, Perl, or similar. Familiarity with leading EDA tools from Synopsys, Cadence, or Siemens (ICC2/Fusion, Innovus...

Location: Markham, ON
Posted Date: 23 Jan 2026

Formal Verification Engineer

or familiarity with formal tools and/or functional verification tools from Synopsys, Cadence or Mentor Graphics ACADEMIC...

Location: Markham, ON
Posted Date: 23 Jan 2026

Silicon Design Engineer

: Python, Tcl, Perl, or similar. Familiarity with leading EDA tools from Synopsys, Cadence, or Siemens (ICC2/Fusion, Innovus...

Location: Markham, ON
Posted Date: 22 Jan 2026

Formal Verification Engineer

or familiarity with formal tools and/or functional verification tools from Synopsys, Cadence or Mentor Graphics ACADEMIC...

Location: Markham, ON
Posted Date: 22 Jan 2026

Senior Physical Design Engineer - P&R

experience in the ASIC digital P&R field. Recent experience with leading EDA tools, advanced flows and techniques (Synopsys...

Location: Toronto, ON
Posted Date: 18 Jan 2026
Salary: $130000 - 180000 per year

RTL Design Engineer

: Synthesis Constraints for Synopsys Preferred: Fusion Compiler OK: Design Compiler Knowledge of Formal Checking tools...

Company: Wipro
Location: Toronto, ON
Posted Date: 14 Jan 2026
Salary: $77000 - 120000 per year

Senior ASIC Design Engineer, Compute DSP/AI Processors (multiple levels)

Collaborate with software teams to develop new features Use of various design tools (VCS Simulator, Synopsys Compiler , Linting..., design tools (Synopsys, Cadence, Mentor) and flows, Understand high performance processor design for high speed and low...

Company: Qualcomm
Location: Markham, ON
Posted Date: 14 Jan 2026
Salary: $124200 - 174200 per year

Senior Physical Design Engineer - P&R

and techniques (Synopsys/Cadence) Good understanding of advanced FinFET technology nodes, DRC rules and specific P&R requirements...

Location: Ottawa, ON
Posted Date: 14 Jan 2026
Salary: $130000 - 180000 per year

ASIC Design and Implementation Engineer – Compute DSP/AI Processors

and implementation skills using several of the following languages and tools Synthesis: Synopsys FC (or DCG/NXT), Cadence Genus...

Company: Qualcomm
Location: Markham, ON
Posted Date: 31 Dec 2025
Salary: $104900 - 154900 per year

Physical Design Engineer (DSP)

cores. Hands-on expertise with: Place & Route tools: Cadence Innovus and/or Synopsys ICC2/Fusion Compiler Timing... closure: Synopsys PrimeTime Physical verification: DRC/LVS sign-off flows Strong understanding of DFT, multi-mode/multi...

Company: Qualcomm
Location: Markham, ON
Posted Date: 20 Dec 2025

Tile-Level Place & Route (PnR) - Physical Design Engineer

. Execute PnR flows from netlist to GDSII using industry-standard EDA tools (Cadence Innovus, Synopsys ICC2/FC). Timing & Power...-on PnR experience. Advanced technology nodes (7nm, 5nm, or below). Tools: Cadence Innovus, Synopsys FC, PrimeTime, Calibre...

Location: Markham, ON
Posted Date: 18 Dec 2025

Tile-Level Place & Route (PnR) - Physical Design Engineer

flows from netlist to GDSII using industry-standard EDA tools (Cadence Innovus, Synopsys ICC2/FC). Timing & Power Analysis...-on PnR experience. Advanced technology nodes (7nm, 5nm, or below). Tools: Cadence Innovus, Synopsys FC, PrimeTime, Calibre...

Location: Markham, ON
Posted Date: 17 Dec 2025

Timing & SDC Design Engineer

in ASIC design, Synopsys design constraint (SDC) creation, and static timing analysis (STA). You are a collaborative team... tools (Synopsys PrimeTime, Cadence Tempus). Familiarity with synthesis tools (Design Compiler) and constraint validation...

Location: Markham, ON
Posted Date: 13 Dec 2025

Timing & SDC Design Engineer

. You have deep experience in ASIC design, Synopsys design constraint (SDC) creation, and static timing analysis (STA... tools (Synopsys PrimeTime, Cadence Tempus). Familiarity with synthesis tools (Design Compiler) and constraint validation...

Location: Markham, ON
Posted Date: 12 Dec 2025

Controller Modelling Developer – Virtual ECU Prototyping

the shelf EDA toolchains such as Synopsys Virtualizer and ASTC vLAB Expertise in various programming languages (C, C...

Company: General Motors
Location: Markham, ON
Posted Date: 11 Dec 2025

Principal Mixed Signal Design Engineer

electronic design automation (EDA) tools for schematic capture, simulation, layout, and verification, such as Cadence, Synopsys...

Company: Marvell
Location: Toronto, ON
Posted Date: 06 Dec 2025