System on Chip (SOC) Digital Design Senior Principal Engineer, who will be responsible for end to end SOC design development... and technical support Enable DV, DFT, PD, FPGA and emulation teams for SOC development Support to Software teams for early...
Job Requirements Job Description Job Title: Senior Gate-Level Simulation (GLS) Verification Engineer Location... skilled and meticulous Gate-Level Simulation (GLS) Verification Engineer to serve as the last line of defense before silicon...
from senior engineers Ensure quality delivery as approved by the senior engineer or project lead Measures of Outcomes...) in EE/EC/ECC Engineering As a member of the Design Verification [Pre-Silicon DV] Team for NXP WCS/SCE...