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Keywords: Senior ASIC Timing Engineer, Location: Santa Clara, CA

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Senior Principal Digital IC Design Engineer

, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As a Senior Principal Digital IC... Design Engineer at Marvell, you will be part of the DCE – Connectivity Business Group, contributing to the development...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 12 Nov 2025

Senior Principal Engineer, Physical Design

and execution, Marvell’s custom Processor/ASIC solution offers a differentiated approach with a best-in-class portfolio of data... Expect As a senior leader in the central physical design team, you will: Shape the long-term vision for physical design...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 13 Dec 2025

Senior SRAM Circuit Design Engineer

We are looking for a Senior SRAM Circuit Designer! NVIDIA has continuously reinvented itself over two decades... and optimize design for power, timing, area and yield You'll make the layout floorplan and work with layout designers to optimize...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 20 Nov 2025

Senior Staff Engineer, Physical Design

and execution, Marvell’s custom Processor/ASIC solution offers a differentiated approach with a best-in-class portfolio of data.../support designs with multi-voltage designs through all aspects of implementation (place and route, static timing, physical...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 06 Dec 2025
Salary: $124420 - 186400 per year

Senior Engineer, Physical Design

and execution, Marvell’s custom Processor/ASIC solution offers a differentiated approach with a best-in-class portfolio of data... performance by running timing analysis, verifying a robust power grid by performing EMIR analysis, etc. There are many sign-off...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 06 Dec 2025
Salary: $89360 - 133900 per year

Senior Principal Digital IC Design Engineer

, place and route, and timing signoff. Collaborate with the verification team on pre-silicon verification tasks... such as AXI, HBM, Ethernet, PCIe, and D2D. Experience in micro-architecture of complex custom/ASIC products, focusing...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 30 Oct 2025

SOC IP Methodology Engineer - Custom SOC

Nvidia is hiring a Senior SOC/IP Methodology Engineer to help design and architect next generation custom SoC/IP... expert, able to traverse from Synthesis to final design closure (timing and layout) involving latest EDA technologies...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 21 Jan 2026

Principal Technical IP Engineer - Manage 3rd Party IP Integration - DDR/LPDDR/GDDR/HBM/eMMC memory

, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As a Hardware Design Senior Staff... Engineer with Marvell, you’ll be a member of the Central Engineering business group. Central Engineering is the center hub...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 16 Nov 2025
Salary: $143200 - 214500 per year

Digital IC design Engineer

, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As a Hardware Design Senior Staff... Engineer with Marvell, you’ll be a member of the Custom compute and solutions group. Our design team works on state-of-the-art...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 08 Nov 2025
Salary: $121400 - 181800 per year

Physical Design Methodology Engineer

first pass silicon success. THE PERSON: A successful candidate will work with senior silicon design engineers. The... level timing analysis with bleeding edge STA methodologies Full chip / sub system level Clock tree synthesis and advanced...

Posted Date: 09 Nov 2025