Job Title: ASIC/RTL Design Engineer Duration: 12+ months Location: Santa Clara, CA Key Responsibilities: Develop... the root cause, work with RTL and firmware engineers to resolve design defects and correct any test issues. Work...
JOB DUTIES: Responsible for RTL design using Verilog HDL for implementation and debug. Read and comprehend Analog Macro... in RTL, with experience in LDOs, BGs and EMC Ability to run and debug LECC for design Run quality check tool...
JOB DUTIES: Responsible for RTL design using Verilog HDL for implementation and debug. Read and comprehend Analog Macro... in RTL, with experience in LDOs, BGs and EMC Ability to run and debug LECC for design Run quality check tool...