. Responsibilities * Design and implement RTL for digital/analog blocks using Verilog/SystemVerilog. * Execute synthesis, floorplanning...) and produce clear technical documentation. SKILLS Must have * 4-8y exp * RTL design implementation of Digital/Analog blocks...
. Implement timing closure strategies, including ECOs, buffer insertion, and cell sizing. Collaborate with RTL, Physical Design...Job Description We are looking for a Staff/Senior Staff Engineer with deep expertise in Logic Synthesis and/Or Static...
your career. LEAD SILICON DESIGN ENGINEER THE ROLE: This exciting position in AMD's Silicon IP solutions & SOC group... u-architecture from the archtiecture defintion Evaluating and executing design and development plans for IPs RTL design, IP...
your career. MTS SILICON DESIGN ENGINEER THE ROLE: The focus of this role is to plan, build, and execute the verification... of new and existing features for AMD’s graphics processor IP, resulting in no bugs in the final design. THE PERSON...
FPGA Design – Lead Engineer Experience: 8–15 Years Location: Hyderabad Employment Type: Full-time Availability...: Immediate / Short Notice Role Overview We are seeking an FPGA Design Lead Engineer with deep expertise in digital logic...
FPGA Design – Senior Engineer Experience: 6–9 Years Location: Hyderabad Employment Type: Full-time Positions: 7... Availability: Immediate / Short Notice Role Overview We are looking for a Senior FPGA Design Engineer with strong digital...
FPGA Design Engineer Experience: 4–6 Years Location: Hyderabad Employment Type: Full-time Availability: Immediate... / Short Notice Role Overview We are seeking an FPGA Design Engineer with strong digital design fundamentals and hands...
SoC Design Lead Engineer – ASIC / SoC (ARM-Based Platforms) Experience: 10–15 Years Location: Bengaluru, India..., or a related field. Role Overview We are seeking an accomplished SoC Design Lead Engineer to provide technical ownership...
SoC Design Engineer – Junior Level (ASIC / SoC) Experience: 3–5 Years Location: Bengaluru, India Employment... discipline. Role Overview We are seeking a SoC Design Junior Engineer with hands-on experience in ARM-based SoC and subsystem...
Alternate Job Titles: Staff Engineer - ASIC Physical Design We Are: At Synopsys, we drive the innovations that shape the.... You Are: You are an accomplished engineer with a passion for innovation in the semiconductor industry. Your expertise in ASIC physical design...
: We are searching for a Principal HBM IO Architecture Design engineer own the development of the PHY IO on the interface die in HBM... Product Engineering or equivalent preferred D2D design experience is a plus Familiar with IP level verification and strong RTL...
Engineer - ASIC Physical Design We Are: At Synopsys, we drive the innovations that shape the way we live and connect...,-age,-military-veteran-status,-or-disability. /span /p custom_fields.CareerAreas-ASIC-Physical-Design custom_fields...
.Multikeywordfacets-Hardware"> Join our Talent Community! . Find Jobs For Where? Search Jobs High-Speed Analog Design Engineer.... You Are: You are an accomplished analog design engineer with a passion for pushing the boundaries of high-speed connectivity. You thrive on solving...
and create design architecture spec documents for the new features Assist in design and development of schematics and/or RTL...Contribute to the Development of New Memory Products by Assisting with Algorithm Design and Firmware Development...
and create design architecture spec documents for the new features Assist in design and development of schematics and/or RTL...Contribute to the Development of New Memory Products by Assisting with Algorithm Design and Firmware Development...
understanding and hands-on experience in lower node technologies. (5nm or below) Drive the design and implementation of large... design blocks from initial concept through to tape-out. Execute synthesis for high-speed designs and lead the Place...
at architecture level, RTL level. THE PERSON: You have a passion for modern, complex processor architecture, digital design... optimization opportunities, generate power optimal recipe for physical design teams, help design teams build power optimal design...
. * Solid understanding of functional coverage and code coverage metrics and how to drive closure. * Good RTL understanding... (Verilog/VHDL) and ability to read and debug design source. * A good knowledge of simulation flow * Working experience...
understanding and hands-on experience in lower node technologies. (5nm or below) Drive the design and implementation of large... design blocks from initial concept through to tape-out. Execute synthesis for high-speed designs and lead the Place...
Own end-to-end IP and SOC development from micro-architecture through RTL design, integration, and silicon support. Own... IP and Subsystem design from scratch, ensuring high-quality, reusable RTL. Drive SoC integration, including CDC, lint...