to RTL (Verilog) design for next generation Snapdragon Display Processors. Integration of external IP's and design... for RTL Linting, power analysis, and CDC Analysis. Develop a strong foundation in good digital design practices. Participate...
tests Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects..._ Responsibilities: THE ROLE: As a Graphics Multimedia IP Verification Engineer - Methodology & Infrastructure Development, the main...
failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test..._ THE ROLE: As a Graphics Multimedia IP Verification Engineer - Methodology & Infrastructure Development, the main focus...
_ Responsibilities: THE ROLE: AMD is seeking an ASIC Design STA Engineer to support the development of large SoCs featuring multiple... with both front-end (RTL) and back-end (Synthesis and P&R) design flows is preferred. THE PERSON: We are looking for high-energy...
_ THE ROLE: AMD is seeking an ASIC Design STA Engineer to support the development of large SoCs featuring multiple physical... with both front-end (RTL) and back-end (Synthesis and P&R) design flows is preferred. THE PERSON: We are looking for high-energy...
part of Qualcomm's growth and momentum. We are looking for a seasoned ASIC Design Engineer who will bring power expertise... of ASIC hardware design and/or implementation experience. Expertise with Verilog/VHDL RTL design languages and ability...
: We are seeking a highly motivated DSP/NPU ML Modeling Engineer to join our team in developing and optimizing DSP algorithms... model, correlating the performance model to RTL model, analyzing workload, defining ISA and features, and so on. The...
, hardware, or test Experienced in RTL level ASIC design Experience in Verilog, System Verilog, and working in the Windows... / Firmware MEC / CP uCode design and development environment for our next generation Machine Intelligence GPUs...
, hardware, or test Experienced in RTL level ASIC design Experience in Verilog, System Verilog, and working in the Windows... / CP uCode design and development environment for our next generation Machine Intelligence GPUs. This is an important role...
what’s next! THE ROLE: We are in need of a Silicon Debug Engineer to debug top post-silicon issues with some of AMD’s major APU... customer questions about design and software functionality Assist with customer feature enablement Drive debug with internal...
what’s next! THE ROLE: We are in need of a Silicon Debug Engineer to debug top post-silicon issues with some of AMD’s major APU... customer questions about design and software functionality Assist with customer feature enablement Drive debug with internal...