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Keywords: RTL Design Engineer, Location: California

Page: 7

Senior Digital Design Engineer - High-Speed I/O and Photonics

, which then will be translated into RTL and firmware designs. For backend design, you will define, build synthesis constraints and drive timing... design, proficient with front-end design flow and tools. Deep understanding of Verilog or System Verilog, logic design...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 28 Sep 2025

Low Power Design/Methodology Engineer

. Perform RTL design, simulation, synthesis, timing analysis, lint check, clock domain crossing check, conformal low power check... cycle from RTL to GDS. Analyze how a new methodology will affect different phases of the design/verification cycle and work...

Company: Qualcomm
Location: San Diego, CA
Posted Date: 23 Sep 2025

System IP Design Verification Engineer

solutions, Offshore Design Centers (ODCs), and staff augmentation across key areas like RTL Design, UVM Verification, Emulation..., FPGA Validation, DFT, RTL-to-GDSII, Physical Design, Mask Layout, and Silicon Bring-up. Our embedded services include...

Company: Prodapt
Location: San Jose, CA
Posted Date: 23 Sep 2025

System IP Design Verification Engineer

services. We offer turnkey solutions, Offshore Design Centers (ODCs), and staff augmentation across key areas like RTL Design..., UVM Verification, Emulation, FPGA Validation, DFT, RTL-to-GDSII, Physical Design, Mask Layout, and Silicon Bring-up...

Company: Prodapt
Location: San Jose, CA
Posted Date: 23 Sep 2025

Principal Silicon Design Engineer

improvements across teams to improve overall program execution PREFERRED EXPERIENCE: Proficiency with Verilog/VHDL RTL design... and IP level design, SOC architecture and implementation strategies. THE PERSON: Excellent communication and presentation...

Posted Date: 20 Sep 2025

Senior CPU Physical Design Engineer

with microarchitecture and RTL design team to implement the designs, meeting aggressive power, area and performance goals using industry... and delivers GDS. Optimizes the design at various stages from RTL to GDS to meet timing, power and area goals. Validates the...

Company: Qualcomm
Location: San Diego, CA
Posted Date: 19 Sep 2025
Salary: $132009 - 183700 per year

Digital Design Engineer

-chip integration timelines. Perform RTL design and coding using Verilog/SystemVerilog. Conduct functional and performance.... Required skills/experience in: Hardware RTL low power design and optimization; Scalable mesh network design; Complex stage pipeline...

Company: OmniVision
Location: Irvine, CA
Posted Date: 18 Sep 2025
Salary: $125000 - 138000 per year

Sr. ASIC Design Verification Engineer, Project Kuiper

a state of the art verification environment to facilitate testing of the RTL against reference Matlab/C models · Develop... formal verification of complex blocks to ensure functional correctness · Work with the design and communication systems team...

Company: Amazon
Location: San Diego, CA
Posted Date: 14 Sep 2025

ASIC Design Engineer, Cloud-Scale Machine Learning Acceleration team

of the ASIC design team, you will implement and deliver high performance, area and power efficient RTL to achieve design....S. in Electrical Engineering or related technical field - 5+ years in RTL design for SOC - 5+ years in VLSI engineering - 5+ years...

Company: Amazon
Location: Cupertino, CA
Posted Date: 11 Sep 2025

Senior Digital Design Engineer - High-Speed I/O and Photonics

, which then will be translated into RTL and firmware designs. For backend design, you will define, build synthesis constraints and drive timing... design, proficient with front-end design flow and tools. Deep understanding of Verilog or System Verilog, logic design...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 10 Sep 2025

Implementation Timing / STA Design Engineer

timing analysis. Collaborate closely with RTL design and physical design teams to identify timing requirements... and bottlenecks. Generate/review, and validate clock domain crossing and design constraints to achieve timing closure of complex SoC...

Company: Qualcomm
Location: San Diego, CA
Posted Date: 05 Sep 2025

VLSI Design Engineer for Server / Data Center Products

team responsible for RTL Design, flows and methodology for high performance ASICs in the latest process nodes for High... is looking for bright ASIC engineers with excellent analytical and technical skills. Besides solid ASIC and/or FPGA design experience...

Company: Qualcomm
Location: San Diego, CA
Posted Date: 04 Sep 2025

Staff Logic Circuit Design Engineer

experience in digital design Strong fundamental knowledge of digital design and RTL development Good understanding on timing/area...

Company: Micron
Location: Folsom, CA
Posted Date: 23 Aug 2025

Low Power Design/Methodology Engineer

. Perform RTL design, simulation, synthesis, timing analysis, lint check, clock domain crossing check, conformal low power check... cycle from RTL to GDS. Analyze how a new methodology will affect different phases of the design/verification cycle and work...

Company: Qualcomm
Location: San Diego, CA
Posted Date: 22 Aug 2025

Graduate - Senior Engineer Digital IC Design

you will: Design and implement digital circuits for automotive electronic application Develop digital architectures that meet... (RTL) code, implement and simulate digital designs to ensure functionality and performance requirements...

Company: Infineon
Location: San Jose, CA
Posted Date: 20 Aug 2025

SRAM Circuit Design Engineer

team to create optimal GDS. - Verify extracted GDS meets design specifications. - Backend verification, IR/EM - Write RTL... and high performance. Knowledge of Cache design/architecture, memory hierarchy is a huge plus. Working knowledge of RTL...

Company: Apple
Location: Santa Clara, CA
Posted Date: 16 Aug 2025

SoC Design Engineer

, micro architecture design, RTL design and hardware/software co-simulation; Work with algorithm and application engineers...Be responsible for digital design of image sensor, SoC integration and IP design, analysis, integration, and validation...

Company: OmniVision
Location: Santa Clara, CA
Posted Date: 13 Aug 2025
Salary: $151091 - 155000 per year

Analog & Mixed Signal IP Design & Validation Engineer

architecture, RTL design, verification, signal integrity, packaging, board design, DFT and ESD to ensure seamless PHY integration...In this role you will contribute to the design, integration and validation of high-performance analog and mixed-signal...

Company: Apple
Location: Cupertino, CA
Posted Date: 24 Jul 2025

GPU Physical Design Engineer

, being responsible for implementing complete chip design from RTL to tapeout. Description - Work closely with the FE team... to understand the design architecture to drive optimal floorplanning and physical implementation through early RTL feedback. Use...

Company: Apple
Location: Santa Clara, CA
Posted Date: 17 Jul 2025

SoC Design Engineer

Familiar with digital design flow, including verilog RTL coding/simulation, synthesis, static timing analysis..., and formality Knowledge of high performance and low power design techniques. Knowledge of FPGA and emulation platforms. Knowledge...

Company: OmniVision
Location: Santa Clara, CA
Posted Date: 16 Jul 2025
Salary: $110600 - 140000 per year