Find your dream job now!

Click on Location links to filter by Job Title & Location.
Click on Company links to filter by Company & Location.
For exact match, enclose search terms in "double quotes".

Keywords: RTL/Logic Design Engineer, Location: Santa Clara, CA

Page: 2

Principal Engineer, Physical Design

RTL, verification, and CAD, to ensure cohesive and optimized design execution. Mentor and coach senior and junior... opportunity to work on both the physical design and methodology for future designs of our next-generation, high-performance...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 29 Oct 2025
Salary: $146850 - 220000 per year

Senior ASIC Design Engineer – Clocks IP

and ability to collaborate with multiple teams. Experience in RTL design (Verilog), verification and logic synthesis... of timing closure to innovate and implement new Clocking topologies in RTL. Collaborate with Physical design and timing team...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 29 Oct 2025

CPU Design Verification Engineer

Verification Engineer owning the verification of a certain area of functionality in a CPU design, you will have the following... responsibilities: • Work closely with architecture and RTL designers on verifying the functionality correctness of the design • Develop...

Company: Apple
Location: Santa Clara, CA
Posted Date: 29 Oct 2025

CPU Design Verification Engineer

Verification Engineer owning the verification of a certain area of functionality in a CPU design, you will have the... checkers or C-base transactor to verify the design Minimum Qualifications Minimum BS Academic experience in digital logic...

Company: Apple
Location: Santa Clara, CA
Posted Date: 29 Oct 2025
Salary: $126800 - 190900 per year

CPU Design Verification Engineer

Verification Engineer owning the verification of a certain area of functionality in a CPU design, you will have the following... responsibilities: • Work closely with architecture and RTL designers on verifying the functionality correctness of the design • Develop...

Company: Apple
Location: Santa Clara, CA
Posted Date: 28 Oct 2025

CPU Design Timing Engineer

. Description As the CPU Design Timing Engineer, you will be responsible for the timing closure of the project. Responsibilities include... Understanding of physical design tools and methodology including logic synthesis, PnR, parasitic extraction, logic equivalence...

Company: Apple
Location: Santa Clara, CA
Posted Date: 28 Oct 2025

Senior Circuit Design Engineer

We are now looking for a Senior Circuit Design Engineer! NVIDIA stands at the intersection of hardware excellence... the design and physical implementation of custom digital IPs from RTL to layout using industry standard tools and custom...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 10 Oct 2025

Senior ASIC Physical Design Engineer, Netlisting

of hardware architecture and hands-on skills in RTL/logic design for timing closure. Experience in clock-domain-crossing..., to amplify human inventiveness and intelligence. We are now looking for a motivated Senior ASIC Physical Design Engineer...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 08 Oct 2025

Digital IC Design Staff Engineer

design and application-specific integrated circuit (ASIC) design flows. Perform RTL coding and functional verification.... Analyze and develop the functionality of IC design by utilizing the knowledge of logic design and related very-large-scale...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 07 Oct 2025
Salary: $105470 - 158000 per year

Senior ASIC Design Engineer (NetSec)

specifications. Design SystemVerilog RTL that meets area, performance, and power targets. Verify your blocks with simulation... coverage, and add design-for-debug features. Partner with physical-design teams: review synthesis/timing reports, rewrite RTL...

Location: Santa Clara, CA
Posted Date: 17 Dec 2025

Senior ASIC Design Engineer (NetSec)

specifications. Design SystemVerilog RTL that meets area, performance, and power targets. Verify your blocks with simulation... coverage, and add design-for-debug features. Partner with physical-design teams: review synthesis/timing reports, rewrite RTL...

Location: Santa Clara, CA
Posted Date: 17 Dec 2025

Senior ASIC Design Engineer

design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO...NVIDIA is seeking best-in-class ASIC Design Engineers to design and implement the world’s leading SoC's and GPU...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 10 Dec 2025

DFT Design Engineer

to: Develops the logic design, register transfer level (RTL) coding, simulation, and provides DFT timing closure support as well..., and methods to write and generate RTL and structural code to integrate DFT. Optimizes logic to qualify the design to meet power...

Company: Intel
Location: Santa Clara, CA
Posted Date: 10 Dec 2025

DFT Design Engineer

to: Develops the logic design, register transfer level (RTL) coding, simulation, and provides DFT timing closure support as well..., and methods to write and generate RTL and structural code to integrate DFT. Optimizes logic to qualify the design to meet power...

Company: Intel
Location: Santa Clara, CA
Posted Date: 10 Dec 2025

Senior Staff Engineer, Physical Design

across various disciplines such as Digital/RTL/Analog to ensure design convergence and integration in a timely manner Implement... verification) using industry standard EDA tools Work with RTL design teams to drive assembly and design closure. Provide...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 06 Dec 2025
Salary: $124420 - 186400 per year

Senior ASIC Physical Design Engineer, Cache Coherent Interconnects

while collaborating closely with the logic design team on micro-architecture definition and feasibility. This position offers you the... future of computing. What you'll be doing: As a member of our CPU team, you'll be a liaison between Logic design...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 21 Nov 2025

ASIC Design Engineer - New College Grad 2026

development (Verilog). Good understanding of ASIC design flow including RTL design, verification, logic synthesis and timing... and deliver high performance, area and power efficient RTL to achieve design targets and specifications. Analyze architectural...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 19 Nov 2025
Salary: $96000 - 161000 per year

Physical Design Methodology Engineer

, you will work closely with the architecture, IP design, RTL design, CAD, silicon technology teams and product engineers to achieve... related to Artificial Intelligent/ High Performance Computing SOCs . As a member of the Physical design and SOC teams...

Posted Date: 09 Nov 2025

SRAM Circuit Design Engineer

the following: - Design and implement custom digital circuits for SRAM design. - Work with an extraordinary logic... team to create optimal GDS. - Verify extracted GDS meets design specifications. - Backend verification, IR/EM - Write RTL...

Company: Apple
Location: Santa Clara, CA
Posted Date: 15 Oct 2025

AI/ML Design Verification Methodology Lead Engineer

: As a AI/ML Design Verification Methodology Lead, will involve in developing and implementing verification strategies... closely with design, architecture, and software teams. Job Responsibilities This role involve defining and driving AI/ML...

Company: Qualcomm
Location: Santa Clara, CA
Posted Date: 10 Oct 2025