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Keywords: Physical Design SoC Clock Engineer, Location: USA

Page: 2

Physical Design Engineer

hardworking Physical Design Engineer. As a member of our wide-ranging group, you will have the rare and great opportunity to craft.... Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL...

Company: Apple
Location: Cupertino, CA
Posted Date: 23 Oct 2025

Physical Design Engineer

hardworking Physical Design Engineer. As a member of our wide-ranging group, you will have the rare and great opportunity to craft.... Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL...

Company: Apple
Location: Beaverton, OR
Posted Date: 23 Oct 2025

Physical Design Engineer

hardworking Physical Design Engineer. As a member of our wide-ranging group, you will have the rare and great opportunity to craft.... Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL...

Company: Apple
Location: Cupertino, CA
Posted Date: 22 Oct 2025
Salary: $126800 - 190900 per year

Principal Physical Design Engineer

's Central Physical Design team, you’ll provide backend design services to Marvell's SoC groups, working across a variety... and targeted at the forefront of data infrastructure. What You Can Expect As a Principal Physical Design Engineer specializing...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 04 Oct 2025
Salary: $146850 - 220000 per year

GPU Physical Design Engineer

simulations. Advanced experience in global and local clocking topologies. 6+ years of hands on SOC Clock Implementation... etc. We are looking for Graphics Hardware Clocking/Engineer to join the team. The primary responsibilities for this role will include...

Company: Intel
Location: Folsom, CA
Posted Date: 21 Dec 2025

Principal Physical Design Engineer

Responsible for SOC Top Level Design Planning and partitioning strategies. Responsible for RTL to GDS implementation... in Physical Design domain. Coordinate with CAD, RTL/Design teams/DFT, Architecture team, Power & Performance team, Technology team...

Company: Microsoft
Location: Hillsboro, OR
Posted Date: 19 Dec 2025

Senior Principal Engineer, Physical Design

SoC programs, overseeing synthesis, floorplanning, power grid design, place and route, clock tree synthesis, timing... and scaling physical design teams, managing complex SoC projects, and delivering high-quality tapeouts under aggressive schedules...

Company: Marvell
Location: Morrisville, NC
Posted Date: 13 Dec 2025

Senior Principal Engineer, Physical Design

SoC programs, overseeing synthesis, floorplanning, power grid design, place and route, clock tree synthesis, timing... and scaling physical design teams, managing complex SoC projects, and delivering high-quality tapeouts under aggressive schedules...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 12 Dec 2025

Physical Design Methodology Engineer

related to Artificial Intelligent/ High Performance Computing SOCs . As a member of the Physical design and SOC teams... RESPONSIBLITIES: Physical design and signoff methodology development for advanced nodes and High performance Automation to improve...

Posted Date: 09 Nov 2025

Senior Formal Verification Engineer – AI SoC Development

corrective measures. Collaborate with architects, RTL developers, and physical design teams to improve verification of complex... understanding of digital design concepts, clock domain crossings, and low-power design techniques. Familiarity with UVM-based...

Company: Intel
Location: Folsom, CA
Posted Date: 21 Dec 2025

Cellular SoC Static Timing Analysis Engineer

, you will have responsibilities spanning various aspects of SOC design: Full chip and block level timing closure ownership throughout the entire... and validating SDC constraints, collaborating closely with RTL, synthesis, and physical design teams to resolve timing issues. Own...

Company: Apple
Location: San Diego, CA
Posted Date: 30 Oct 2025

Cellular SoC Static Timing Analysis Engineer

, you will have responsibilities spanning various aspects of SOC design: Full chip and block level timing closure ownership throughout the entire... and validating SDC constraints, collaborating closely with RTL, synthesis, and physical design teams to resolve timing issues. Own...

Company: Apple
Location: San Diego, CA
Posted Date: 30 Oct 2025

SoC Integration Engineer

. Description As a SOC Integration Engineer, you will have responsibilities to design IPs. - Working with other specialists that are members... of the SoC Design, SoC Design Verification, System Verification, STA, and Physical Design teams to implement designs/flows...

Company: Apple
Location: Cupertino, CA
Posted Date: 17 Oct 2025

SoC Integration Engineer

. Description As a SOC Integration Engineer, you will have responsibilities to design IPs. - Working with other specialists that are members... of the SoC Design, SoC Design Verification, System Verification, STA, and Physical Design teams to implement designs/flows...

Company: Apple
Location: Cupertino, CA
Posted Date: 17 Oct 2025
Salary: $126800 - 190900 per year

SoC Architecture Engineer

with CPU, GPU, memory controller, IP and SOC design, physical design, and product engineering teams. You will own SoC-level... distribution, and power intent definition (UPF/CPF). Proven track record of low-power SoC design (clock gating, power gating...

Posted Date: 02 Oct 2025

Sr. ASIC Design Engineer (Silicon Engineering)

ultimate goal of enabling human life on Mars. SR. ASIC DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging... all aspects of the design are covered and verified Provide timing constraint for those IPs and support the physical...

Company: SpaceX
Location: USA
Posted Date: 20 Dec 2025

Principal Digital IC Design Engineer – Custom Compute Solutions

. Collaborate with architecture, verification, and physical design teams to deliver high-quality, production-ready IP. Drive...-standard EDA tools for design. Experience with low-power design techniques, clock-domain crossing, and design-for-test (DFT...

Company: Marvell
Location: Westborough, MA
Posted Date: 18 Dec 2025
Salary: $165000 - 244200 per year

Design Engineer - Floorplanner

, from concept through production. Role Overview This Floorplanning Engineer role focuses on chip-level physical architecture.... Drive macro placement, power grid design, clock distribution planning, pin placement, and feedthrough optimization...

Company: Broadcom
Location: Fort Collins, CO
Posted Date: 17 Dec 2025

Design Engineer - Chip Floorplanner

, from concept through production. Role Overview This Floorplanning Engineer role focuses on chip-level physical architecture.... Drive macro placement, power grid design, clock distribution planning, pin placement, and feedthrough optimization...

Company: Broadcom
Location: Fort Collins, CO
Posted Date: 16 Dec 2025

Senior ASIC Design Engineer

NVIDIA is looking for a Senior ASIC Design Engineer to join our Memory Subsystem Team! As a Senior ASIC Design... engineer at NVIDIA, you'll join a group of hard-working engineers to design and implement innovative coherent fabrics...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 14 Dec 2025