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Keywords: Memory Design Engineer, Location: Santa Clara, CA

Page: 6

SERDES Validation Director

signaling for Ethernet, CPRI, JESD, and PCIe interfaces. DRAM interfaces include LPDDR5, DDR4/5 memory modules... addressed from an equipment and training perspective. Support high-speed board design, debug and board extraction, definition...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 20 Sep 2025

Performance Modeling Architect- Data Center GPU

_ THE ROLE: As a Fellow/ Sr Fellow level Engineer you will spearhead performance analysis and modeling for AMD datacenter... performance gains in both training and inference pipelines through innovative system design and optimization. You will champion...

Posted Date: 18 Sep 2025

Contract Manufacturing Onsite Team Lead

approach. Rate: $60-65/hr on W2 Job Description: We are looking for a highly skilled Senior Validation Engineer to lead... validation results, ensuring clear communication of findings and recommendations. Work with design and manufacturing teams...

Company: ApTask
Location: Santa Clara, CA
Posted Date: 06 Sep 2025

FVCTO - Formal Verification Architect

and AI platforms. IP design group within DCAI designs Coherent Fabric IP, Memory controller, NOC, PCIE and many fundamental building...). As a Formal Verification Engineer, you will be responsible the following but not limited to: Verify microarchitecture using...

Company: Intel
Location: Santa Clara, CA
Posted Date: 12 Jul 2025