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Keywords: IP Verification Lead, Location: Bangalore, Karnataka

Page: 7

Associate III - VLSI Analog Layout

of RTL Design/Module and provide support to junior engineers in Verification/PD/DFT/Circuit Design/Analog Layout/STA... and on-time On time quality delivery approved by the project lead/manager Measures of Outcomes: * Quality –verified using...

Company: UST
Posted Date: 15 Aug 2025

Associate III - VLSI SRAM ACD

of RTL Design/Module and provide support to junior engineers in Verification/PD/DFT/Circuit Design/Analog Layout/STA... and on-time On time quality delivery approved by the project lead/manager Measures of Outcomes: * Quality –verified using...

Company: UST
Posted Date: 15 Aug 2025

Senior Principal Design Engineer

, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Marvell Compute and Custom Solutions... with a best-in-class portfolio of data infrastructure intellectual property (IP) and a wide-array of flexible business models...

Company: Marvell
Posted Date: 15 Aug 2025

Associate III - VLSI IO

of RTL Design/Module and provide support to junior engineers in Verification/PD/DFT/Circuit Design/Analog Layout/STA... and on-time On time quality delivery approved by the project lead/manager Measures of Outcomes: * Quality –verified using...

Company: UST
Posted Date: 08 Aug 2025

Pre and Post Silicon Validation Engineer

_ MTS SILICON DESIGN ENGINEER Technical 8+ years of experience in Pre & post silicon IP or SOC Validation Working..., ensuring quality and performance. Lead and mentor a team of developers/engineers, fostering technical excellence...

Posted Date: 07 Aug 2025

Associate III - VLSI ML

of RTL Design/Module and provide support to junior engineers in Verification/PD/DFT/Circuit Design/Analog Layout/STA... and on-time On time quality delivery approved by the project lead/manager Measures of Outcomes: * Quality –verified using...

Company: UST
Posted Date: 07 Aug 2025