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Keywords: Design Verification Engineer, Location: San Jose, CA

Page: 6

Silicon Photonics Validation Engineer

your career. THE ROLE: As a Silicon Photonics Validation Engineer in the SerDes Technology team, you will collaborate... with various Product Development Groups, Silicon Design, DFT, Packaging, and interface with key technology partners...

Posted Date: 06 Nov 2025

Senior Mechanical Engineer (NEXTEST; San Jose, CA)

any required design verification. Ability to work with a team is a must. Also, the ability to communicate effectively in a remote... requirements Define and perform verification testing to ensure quality of mechanical design Documentation of components...

Company: Teradyne
Location: San Jose, CA
Posted Date: 24 Oct 2025

Mechanical Engineer (NEXTEST; San Jose, CA)

any required design verification. Ability to work with a team is a must. Also, the ability to communicate effectively in a remote... requirements Define and perform verification testing to ensure quality of mechanical design Documentation of components...

Company: Teradyne
Location: San Jose, CA
Posted Date: 24 Oct 2025
Salary: $106500 - 170400 per year

ATE Product Development Engineer

Development Engineer to be part of New Production Introduction (NPI) product engineering team in AMD. In this position... to production. KEY RESPONSIBILITIES: Design and execute early product evaluation and debug to enable fast time to market...

Posted Date: 17 Oct 2025

Chip Simulation Software Engineer

co-design, enabling early development of the full Sohu software stack. As a software engineer on this team, you will design... hardware-software co-design to deliver world-best performance. The chip simulation team plays a key role in hardware-software...

Company: Etched
Location: San Jose, CA
Posted Date: 15 Oct 2025
Salary: $20000 - 25000 per year

Post-Silicon Validation Engineer

debug. Diagnose complex silicon issues across RTL, firmware, and hardware layers. Collaborate with design, verification...Post-Silicon Validation Engineer About Etched Etched is building AI chips that are hard-coded for individual model...

Company: Etched
Location: San Jose, CA
Posted Date: 11 Oct 2025

ASIC Engineer Sr Staff

Design-for-Test (DFT) Engineer to join our team and contribute to the development of advanced 3nm and beyond networking...ASIC Engineer Sr Staff This role has been designed as ‘Hybrid’ with an expectation that you will work on average 2...

Posted Date: 08 Oct 2025

Technologist - Analog/Mixed-Signal CAD Development Engineer

of concepts and methods for the EDA design environments with focus on analog / mixed signal ASIC design in advanced nodes Tool... of Calibre/Pegasys Physical Verification decks for CMOS PLANAR technologies including DRC, LVS, PERC, FILL LPE and shape...

Company: Western Digital
Location: San Jose, CA
Posted Date: 20 Dec 2025

Technologist - Analog/Mixed-Signal CAD Development Engineer

of concepts and methods for the EDA design environments with focus on analog / mixed signal ASIC design in advanced nodes Tool... of Calibre/Pegasys Physical Verification decks for CMOS PLANAR technologies including DRC, LVS, PERC, FILL LPE and shape...

Company: Western Digital
Location: San Jose, CA
Posted Date: 19 Dec 2025

Senior Space Systems Engineer- San Jose

analysis, system design, trade studies, systems integration and test (verification), validation and interface definition... is required. Responsibilities for this Position: GDMS Sr. Advanced Systems Engineers analyze, design, develop and test GDMS systems to ensure the...

Company: General Dynamics
Location: San Jose, CA
Posted Date: 18 Dec 2025

Sr. Staff Software Development Engineer

will join a team designing and developing Lattice FPGA software tools in San Jose. The candidate will contribute to research, design... - Programming skills (C++ and Python) - Hands-on experience in RTL design and digital design, testbench development, logic...

Location: San Jose, CA
Posted Date: 18 Dec 2025

Sr. Staff Software Development Engineer

++ and Python) - Hands-on experience in RTL design and digital design, testbench development, logic verification, timing closure... designing and developing Lattice FPGA software tools in San Jose. The candidate will contribute to research, design...

Location: San Jose, CA
Posted Date: 18 Dec 2025
Salary: $193000 - 242000 per year

Senior Space Systems Engineer- San Jose

analysis, system design, trade studies, systems integration and test (verification), validation and interface definition... is required. Responsibilities for this Position GDMS Sr. Advanced Systems Engineers analyze, design, develop and test GDMS systems to ensure the...

Company: General Dynamics
Location: San Jose, CA
Posted Date: 17 Dec 2025

Contract Hardware Engineer Mid

(Palladium) and/or Synopsys HAPS-100 Emulation expertise Learn/understand the testbench architecture Strong in Design... Functional Verification (SV/UVM) Software (Test) and Hardware (Emulation) Validation What we are looking for: At-least 2...

Company: LanceSoft
Location: San Jose, CA
Posted Date: 16 Dec 2025

Principal Digital Engineer

of hardware/firmware, RTL design, verification, FPGA prototyping, DFT, and IC qualification. Responsibilities: Chip... in digital logic design Hands-on knowledge and good experience with Verilog/SystemVerilog for digital design and verification...

Location: San Jose, CA
Posted Date: 13 Dec 2025

Sr. Staff Engineer FAE

, driving pre and post design-in activities, contributing to Infineon design-in revenue growth. Develop deep system level... while recommending leading-edge solutions that align with customers' design requirements and future product roadmaps Promote Infineon...

Company: Infineon
Location: San Jose, CA
Posted Date: 02 Dec 2025

Chip Integration Engineer

. 5). Develop Verilog RTL. design verification support, logic synthesis, physical implementation constraints, static... successful candidate will be responsible for various key tasks in the areas of chip integration and RTL design of cutting-edge network...

Company: Broadcom
Location: San Jose, CA
Posted Date: 20 Nov 2025
Salary: $120000 - 192000 per year

Staff Analog Test & Characterization Engineer

design team! Here you'll have the chance to play an important role in terms of validating and characterizing the top-notch... high-speed/high-performance IPs. Responsibilities: Use verification test benches and create lab test scripts and ensure...

Company: Nokia
Location: San Jose, CA
Posted Date: 08 Nov 2025

Senior Validation Engineer

, Design and Cross Functional teams for developing the test automation test/validation cases Setting up the automation..., and SQL Ability to work with cross-functional teams Understand the PCB design layout and schematic capture, ability to pick...

Company: Infineon
Location: San Jose, CA
Posted Date: 31 Oct 2025

Principal Engineer - Cleanroom SME

-class standards. This role provides expert guidance on contamination control, cleanroom design and operation..., and audit readiness. Support the design, layout, and specification of cleanroom systems including HVAC, filtration (HEPA/ULPA...

Company: Jabil
Location: San Jose, CA
Posted Date: 24 Oct 2025