edge I/O SoC in 3 nm processes. This DFX RTL Design Engineer is expected to contribute in : Implementation of SOC DFT... RTL design engineer. As a part of the design team, candidate will be exposed to several IPs including Gbit SERDES, UCIe...
edge I/O SoC in 3 nm processes. This DFX RTL Design Engineer is expected to contribute in : Implementation of SOC DFT... RTL design engineer. As a part of the design team, candidate will be exposed to several IPs including Gbit SERDES, UCIe...