Description: Lead RTL-to-gates implementation using Cadence Genus for GF 22FDX. Drive synthesis strategy, constraint management, and multi-mode multi-corner (MMMC) optimization. Act as a technical mentor for junior engineers, ensuring high...
Description: Lead RTL-to-gates implementation using Cadence Genus for GF 22FDX. Drive synthesis strategy, constraint management, and multi-mode multi-corner (MMMC) optimization. Act as a technical mentor for junior engineers, ensuring high...
Description: Lead RTL-to-gates implementation using Cadence Genus for GF 22FDX. Drive synthesis strategy, constraint management, and multi-mode multi-corner (MMMC) optimization. Act as a technical mentor for junior engineers, ensuring high...
Meta is seeking a highly skilled ASIC Architecture Runtime Development Engineer with experience in hardware modeling, particularly on RISC-V or PCIe architectures. As a key member of our engineering team, you will be responsible for designi...
Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design Verification to build IP and System On Chip (SoC) for data center applications. As a Design Ve...
NVIDIA is looking for a Senior Reset and Boot ASIC Engineer to join our System ASIC team! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 fueled the growth of the PC gaming market, redefined mode...
Job Title: ASIC/RTL Design Engineer Duration: 12+ months Location: Santa Clara, CA Key Responsibilities: Develop/Maintain tests for functional verification. Build the directed and random verification tests, debug test failures to det...
Top skills: RTL coding, TCL coding, Python coding, understanding of different CAD tools (synthesis, lint, CDC, RDC, PrimeTime). JOB DUTIES: The work will expose the designer to a number of IP including ARM cores, Ethernet, DDR, DMA, PCIE...
About Groq Groq delivers fast, efficient AI inference. Our LPU-based system powers GroqCloud™, giving businesses and developers the speed and scale they need. From our Bay Area roots to our growing global presence, we are on a mission to ...
Top skills: RTL coding, TCL coding, Python coding, understanding of different CAD tools (synthesis, lint, CDC, RDC, PrimeTime). JOB DUTIES: The work will expose the designer to a number of IP including ARM cores, Ethernet, DDR, DMA, PCIE...
As a Networking ASIC Engineer on the Infrastructure Silicon team at Meta, you will play a key role in shaping the networking architecture for leading-edge AI training and inference accelerators. You will work closely with other architecture...
Position Title: ASIC/RTL Design Engineer Location: Santa Clara, CA Position Status: Contract Pay Rate: 75/hr Position Description: JOB DUTIES: The work will expose the designer to a number of IP including ARM cores, Ethernet, DDR, DMA,...
Job Description: WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-gener...
Location: San Jose, CA (5 days onsite) Experience: 8 years (Relevant) What candidate will Be Doing: Map multi-million gate SoC designs onto prototyping platforms, creating design partitions, FPGA builds, and testbenches to simulate FPG...
Join the Team That's Redefining Wireless Technology At Tarana, we're more than just a fast-growing tech company—we’re a team of bold innovators on a mission to revolutionize broadband. Our groundbreaking Fixed Wireless Access technology i...
DESCRIPTION Project Kuiper is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low-latency, high-speed broadband connectivity to unserved and underserved communities around the world. The Role: Be...
Meta is hiring ASIC EDA Infrastructure Engineers within our Infrastructure organization. We are looking for individuals with experience in EDA flow and methodology, CAD/automation and ASIC infrastructure to build efficient System on Chip (S...
DESCRIPTION Project Kuiper is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low-latency, high-speed broadband connectivity to unserved and underserved communities around the world. Come work at ...
DESCRIPTION Project Kuiper is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low-latency, high-speed broadband connectivity to unserved and underserved communities around the world. Come work at ...
Meta is hiring an ASIC Engineer within the Infrastructure organization. The Infra Silicon Enablement team is looking for individuals with experience in the entire Silicon Lifecycle to build and scale silicon for data center applications. Yo...