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Keywords: ASIC Timing Engineer, Location: Santa Clara, CA

Page: 3

Senior Staff Engineer, Physical Design

and execution, Marvell’s custom Processor/ASIC solution offers a differentiated approach with a best-in-class portfolio of data.../support designs with multi-voltage designs through all aspects of implementation (place and route, static timing, physical...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 06 Dec 2025
Salary: $124420 - 186400 per year

Senior Engineer, Physical Design

and execution, Marvell’s custom Processor/ASIC solution offers a differentiated approach with a best-in-class portfolio of data... performance by running timing analysis, verifying a robust power grid by performing EMIR analysis, etc. There are many sign-off...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 06 Dec 2025
Salary: $89360 - 133900 per year

Senior SRAM Circuit Design Engineer

and optimize design for power, timing, area and yield You'll make the layout floorplan and work with layout designers to optimize... We will have creative new ideas to support existing tools and flows Develop and Perform timing characterization and circuit verification...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 20 Nov 2025